Lines Matching refs:RC
574 const TargetRegisterClass *RC,
589 if (RI.isSGPRClass(RC)) {
592 if (TargetRegisterInfo::isVirtualRegister(SrcReg) && RC->getSize() == 4) {
601 unsigned Opcode = getSGPRSpillSaveOpcode(RC->getSize());
620 assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected");
622 unsigned Opcode = getVGPRSpillSaveOpcode(RC->getSize());
672 const TargetRegisterClass *RC,
687 if (RI.isSGPRClass(RC)) {
690 unsigned Opcode = getSGPRSpillRestoreOpcode(RC->getSize());
692 if (TargetRegisterInfo::isVirtualRegister(DestReg) && RC->getSize() == 4) {
714 assert(RI.hasVGPRs(RC) && "Only VGPR spilling expected");
716 unsigned Opcode = getVGPRSpillRestoreOpcode(RC->getSize());
1713 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
1714 if (!RC->contains(Reg)) {
1882 const TargetRegisterClass *RC = RI.getRegClass(RCID);
1886 else if (RI.isSGPRClass(RC))
1889 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
1970 const TargetRegisterClass *RC =
1977 RC = TRI->getSubRegClass(RC, MO.getSubReg());
1988 return RI.getCommonSubClass(RC, RI.getRegClass(OpInfo.RegClass)) == RC;
2231 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
2253 RC = VRC;
2255 RC = SRC;
2263 unsigned DstReg = MRI.createVirtualRegister(RC);