Lines Matching refs:Inst
192 bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
194 bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
351 void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
352 void cvtThumbBranches(MCInst &Inst, const OperandVector &);
354 bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
355 bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
396 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
1739 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1742 Inst.addOperand(MCOperand::createImm(0));
1744 Inst.addOperand(MCOperand::createImm(CE->getValue()));
1746 Inst.addOperand(MCOperand::createExpr(Expr));
1749 void addARMBranchTargetOperands(MCInst &Inst, unsigned N) const {
1751 addExpr(Inst, getImm());
1754 void addThumbBranchTargetOperands(MCInst &Inst, unsigned N) const {
1756 addExpr(Inst, getImm());
1759 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1761 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
1763 Inst.addOperand(MCOperand::createReg(RegNum));
1766 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1768 Inst.addOperand(MCOperand::createImm(getCoproc()));
1771 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1773 Inst.addOperand(MCOperand::createImm(getCoproc()));
1776 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1778 Inst.addOperand(MCOperand::createImm(CoprocOption.Val));
1781 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1783 Inst.addOperand(MCOperand::createImm(ITMask.Mask));
1786 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1788 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
1791 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1793 Inst.addOperand(MCOperand::createReg(getReg()));
1796 void addRegOperands(MCInst &Inst, unsigned N) const {
1798 Inst.addOperand(MCOperand::createReg(getReg()));
1801 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1805 Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg));
1806 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg));
1807 Inst.addOperand(MCOperand::createImm(
1811 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1815 Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg));
1818 Inst.addOperand(MCOperand::createImm(
1822 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1824 Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) |
1828 void addRegListOperands(MCInst &Inst, unsigned N) const {
1833 Inst.addOperand(MCOperand::createReg(*I));
1836 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1837 addRegListOperands(Inst, N);
1840 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1841 addRegListOperands(Inst, N);
1844 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1847 Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3));
1850 void addModImmOperands(MCInst &Inst, unsigned N) const {
1855 return addImmOperands(Inst, N);
1857 Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7)));
1860 void addModImmNotOperands(MCInst &Inst, unsigned N) const {
1864 Inst.addOperand(MCOperand::createImm(Enc));
1867 void addModImmNegOperands(MCInst &Inst, unsigned N) const {
1871 Inst.addOperand(MCOperand::createImm(Enc));
1874 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1882 Inst.addOperand(MCOperand::createImm(Mask));
1885 void addImmOperands(MCInst &Inst, unsigned N) const {
1887 addExpr(Inst, getImm());
1890 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1893 Inst.addOperand(MCOperand::createImm(16 - CE->getValue()));
1896 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1899 Inst.addOperand(MCOperand::createImm(32 - CE->getValue()));
1902 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1906 Inst.addOperand(MCOperand::createImm(Val));
1909 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1914 Inst.addOperand(MCOperand::createImm(CE->getValue()));
1917 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1922 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
1925 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1930 Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4)));
1933 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1938 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
1941 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1946 Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
1949 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1954 Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
1957 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1963 Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm)));
1966 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1972 Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val));
1975 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1980 Inst.addOperand(MCOperand::createImm(~CE->getValue()));
1983 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1988 Inst.addOperand(MCOperand::createImm(-CE->getValue()));
1991 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1996 Inst.addOperand(MCOperand::createImm(-CE->getValue()));
1999 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
2001 Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2));
2007 Inst.addOperand(MCOperand::createExpr(SR));
2010 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
2015 Inst.addOperand(MCOperand::createImm(CE->getValue()));
2022 Inst.addOperand(MCOperand::createExpr(SR));
2028 Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue()));
2031 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
2033 Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt())));
2036 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2038 Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt())));
2041 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
2043 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2046 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
2049 Inst.addOperand(MCOperand::createImm(Imm));
2052 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
2059 Inst.addOperand(MCOperand::createExpr(getImm()));
2065 Inst.addOperand(MCOperand::createImm(Val));
2068 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2070 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2071 Inst.addOperand(MCOperand::createImm(Memory.Alignment));
2074 void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2075 addAlignedMemoryOperands(Inst, N);
2078 void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2079 addAlignedMemoryOperands(Inst, N);
2082 void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2083 addAlignedMemoryOperands(Inst, N);
2086 void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2087 addAlignedMemoryOperands(Inst, N);
2090 void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2091 addAlignedMemoryOperands(Inst, N);
2094 void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2095 addAlignedMemoryOperands(Inst, N);
2098 void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2099 addAlignedMemoryOperands(Inst, N);
2102 void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2103 addAlignedMemoryOperands(Inst, N);
2106 void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2107 addAlignedMemoryOperands(Inst, N);
2110 void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2111 addAlignedMemoryOperands(Inst, N);
2114 void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2115 addAlignedMemoryOperands(Inst, N);
2118 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2133 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2134 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2135 Inst.addOperand(MCOperand::createImm(Val));
2138 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2148 Inst.addOperand(MCOperand::createReg(0));
2149 Inst.addOperand(MCOperand::createImm(Val));
2152 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2158 Inst.addOperand(MCOperand::createExpr(getImm()));
2159 Inst.addOperand(MCOperand::createReg(0));
2160 Inst.addOperand(MCOperand::createImm(0));
2176 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2177 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2178 Inst.addOperand(MCOperand::createImm(Val));
2181 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2186 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2187 Inst.addOperand(MCOperand::createImm(Val));
2199 Inst.addOperand(MCOperand::createReg(0));
2200 Inst.addOperand(MCOperand::createImm(Val));
2203 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2209 Inst.addOperand(MCOperand::createExpr(getImm()));
2210 Inst.addOperand(MCOperand::createImm(0));
2221 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2222 Inst.addOperand(MCOperand::createImm(Val));
2225 void addAddrMode5FP16Operands(MCInst &Inst, unsigned N) const {
2231 Inst.addOperand(MCOperand::createExpr(getImm()));
2232 Inst.addOperand(MCOperand::createImm(0));
2243 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2244 Inst.addOperand(MCOperand::createImm(Val));
2247 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2253 Inst.addOperand(MCOperand::createExpr(getImm()));
2254 Inst.addOperand(MCOperand::createImm(0));
2259 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2260 Inst.addOperand(MCOperand::createImm(Val));
2263 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2267 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2268 Inst.addOperand(MCOperand::createImm(Val));
2271 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2274 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2275 Inst.addOperand(MCOperand::createImm(Val));
2278 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2279 addMemImm8OffsetOperands(Inst, N);
2282 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2283 addMemImm8OffsetOperands(Inst, N);
2286 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2290 addExpr(Inst, getImm());
2291 Inst.addOperand(MCOperand::createImm(0));
2297 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2298 Inst.addOperand(MCOperand::createImm(Val));
2301 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2305 addExpr(Inst, getImm());
2306 Inst.addOperand(MCOperand::createImm(0));
2312 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2313 Inst.addOperand(MCOperand::createImm(Val));
2316 void addConstPoolAsmImmOperands(MCInst &Inst, unsigned N) const {
2320 addExpr(Inst, getConstantPoolImm());
2324 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2326 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2327 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2330 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2332 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2333 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2336 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2341 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2342 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2343 Inst.addOperand(MCOperand::createImm(Val));
2346 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2348 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2349 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2350 Inst.addOperand(MCOperand::createImm(Memory.ShiftImm));
2353 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2355 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2356 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2359 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2362 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2363 Inst.addOperand(MCOperand::createImm(Val));
2366 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2369 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2370 Inst.addOperand(MCOperand::createImm(Val));
2373 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2376 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2377 Inst.addOperand(MCOperand::createImm(Val));
2380 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2383 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2384 Inst.addOperand(MCOperand::createImm(Val));
2387 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2395 Inst.addOperand(MCOperand::createImm(Imm));
2398 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2407 Inst.addOperand(MCOperand::createImm(Imm));
2410 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2412 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2413 Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd));
2416 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2418 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2424 Inst.addOperand(MCOperand::createImm(Imm));
2427 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2429 Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask())));
2432 void addBankedRegOperands(MCInst &Inst, unsigned N) const {
2434 Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg())));
2437 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2439 Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags())));
2442 void addVecListOperands(MCInst &Inst, unsigned N) const {
2444 Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
2447 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2449 Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
2450 Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex));
2453 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2455 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2458 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2460 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2463 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2465 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2468 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2473 Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00));
2476 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2482 Inst.addOperand(MCOperand::createImm(Value));
2485 void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
2491 Inst.addOperand(MCOperand::createImm(Value));
2494 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2500 Inst.addOperand(MCOperand::createImm(Value));
2503 void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
2509 Inst.addOperand(MCOperand::createImm(Value));
2512 void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
2517 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2518 Inst.getOpcode() == ARM::VMOVv16i8) &&
2523 Inst.addOperand(MCOperand::createImm(B));
2525 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2536 Inst.addOperand(MCOperand::createImm(Value));
2539 void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
2544 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2545 Inst.getOpcode() == ARM::VMOVv16i8) &&
2550 Inst.addOperand(MCOperand::createImm(B));
2552 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2563 Inst.addOperand(MCOperand::createImm(Value));
2566 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2575 Inst.addOperand(MCOperand::createImm(Imm | 0x1e00));
4757 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
4759 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
4760 ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
4768 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
4769 Inst.addOperand(Inst.getOperand(0));
4770 ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
4773 void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
4776 switch(Inst.getOpcode()) {
4790 switch(Inst.getOpcode()) {
4791 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4792 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4798 switch(Inst.getOpcode()) {
4801 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4805 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4811 switch(Inst.getOpcode()) {
4816 Inst.setOpcode(ARM::t2B);
4823 Inst.setOpcode(ARM::t2Bcc);
4827 ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
4828 ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
5782 static bool RequiresVFPRegListValidation(StringRef Inst,
5785 if (Inst.size() < 7)
5788 if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
5789 StringRef AddressingMode = Inst.substr(4, 2);
5792 AcceptSinglePrecisionOnly = Inst[6] == 's';
5793 AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
6101 static bool checkLowRegisterList(const MCInst &Inst, unsigned OpNo,
6105 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
6106 unsigned OpReg = Inst.getOperand(i).getReg();
6118 static bool listContainsReg(const MCInst &Inst, unsigned OpNo, unsigned Reg) {
6119 for (unsigned i = OpNo, e = Inst.getNumOperands(); i < e; ++i) {
6120 unsigned OpReg = Inst.getOperand(i).getReg();
6129 static bool instIsBreakpoint(const MCInst &Inst) {
6130 return Inst.getOpcode() == ARM::tBKPT ||
6131 Inst.getOpcode() == ARM::BKPT ||
6132 Inst.getOpcode() == ARM::tHLT ||
6133 Inst.getOpcode() == ARM::HLT;
6137 bool ARMAsmParser::validatetLDMRegList(const MCInst &Inst,
6143 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
6144 bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR);
6145 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
6160 bool ARMAsmParser::validatetSTMRegList(const MCInst &Inst,
6166 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
6167 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
6182 bool ARMAsmParser::validateInstruction(MCInst &Inst,
6184 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
6190 if (inITBlock() && !instIsBreakpoint(Inst)) {
6199 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
6215 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
6216 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
6217 Inst.getOpcode() != ARM::t2Bcc)
6220 const unsigned Opcode = Inst.getOpcode();
6225 const unsigned RtReg = Inst.getOperand(0).getReg();
6239 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6245 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
6260 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6261 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6268 const unsigned RmReg = Inst.getOperand(0).getReg();
6277 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6278 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6287 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6288 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6305 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6306 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6328 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6329 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6339 unsigned LSB = Inst.getOperand(2).getImm();
6340 unsigned Widthm1 = Inst.getOperand(3).getImm();
6354 unsigned Rn = Inst.getOperand(0).getReg();
6359 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
6373 if (validatetLDMRegList(Inst, Operands, 3))
6385 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
6391 if (validatetLDMRegList(Inst, Operands, 3))
6396 if (validatetSTMRegList(Inst, Operands, 3))
6403 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
6408 if (validatetLDMRegList(Inst, Operands, 3))
6411 if (validatetSTMRegList(Inst, Operands, 3))
6420 if (!listContainsReg(Inst, 3, ARM::PC))
6437 // this first statement is always true for the new Inst. Essentially, the
6454 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
6458 if (validatetLDMRegList(Inst, Operands, 2, !isMClass()))
6464 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
6468 if (validatetSTMRegList(Inst, Operands, 2))
6474 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
6487 if (validatetSTMRegList(Inst, Operands, 4))
6495 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
6551 unsigned Imm8 = Inst.getOperand(0).getImm();
6552 unsigned Pred = Inst.getOperand(1).getImm();
6822 bool ARMAsmParser::processInstruction(MCInst &Inst,
6825 switch (Inst.getOpcode()) {
6830 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
6834 TmpInst.addOperand(Inst.getOperand(0));
6835 TmpInst.addOperand(Inst.getOperand(1));
6836 TmpInst.addOperand(Inst.getOperand(1));
6839 TmpInst.addOperand(Inst.getOperand(2));
6840 TmpInst.addOperand(Inst.getOperand(3));
6841 Inst = TmpInst;
6848 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
6852 TmpInst.addOperand(Inst.getOperand(1));
6853 TmpInst.addOperand(Inst.getOperand(0));
6854 TmpInst.addOperand(Inst.getOperand(1));
6857 TmpInst.addOperand(Inst.getOperand(2));
6858 TmpInst.addOperand(Inst.getOperand(3));
6859 Inst = TmpInst;
6864 if (Inst.getOperand(1).getReg() != ARM::PC ||
6865 Inst.getOperand(5).getReg() != 0 ||
6866 !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm()))
6870 TmpInst.addOperand(Inst.getOperand(0));
6871 if (Inst.getOperand(2).isImm()) {
6874 unsigned Enc = Inst.getOperand(2).getImm();
6883 const MCExpr *OpExpr = Inst.getOperand(2).getExpr();
6894 TmpInst.addOperand(Inst.getOperand(3));
6895 TmpInst.addOperand(Inst.getOperand(4));
6896 Inst = TmpInst;
6902 if (Inst.getOperand(1).getImm() > 0 &&
6903 Inst.getOperand(1).getImm() <= 0xff &&
6906 Inst.setOpcode(ARM::tLDRpci);
6908 Inst.setOpcode(ARM::t2LDRpci);
6911 Inst.setOpcode(ARM::t2LDRBpci);
6914 Inst.setOpcode(ARM::t2LDRHpci);
6917 Inst.setOpcode(ARM::t2LDRSBpci);
6920 Inst.setOpcode(ARM::t2LDRSHpci);
6929 if (Inst.getOpcode() == ARM::LDRConstPool)
6931 else if (Inst.getOpcode() == ARM::tLDRConstPool)
6933 else if (Inst.getOpcode() == ARM::t2LDRConstPool)
6940 Inst.getOperand(0).getReg() != ARM::PC &&
6941 Inst.getOperand(0).getReg() != ARM::SP) {
6946 if (Inst.getOpcode() == ARM::LDRConstPool) {
6983 TmpInst.addOperand(Inst.getOperand(0)); // Rt
6985 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6986 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6989 Inst = TmpInst;
6997 TmpInst.addOperand(Inst.getOperand(0)); // Rt
7001 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7002 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7003 Inst = TmpInst;
7014 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7015 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7016 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7017 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7018 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7019 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7020 TmpInst.addOperand(Inst.getOperand(1)); // lane
7021 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7022 TmpInst.addOperand(Inst.getOperand(6));
7023 Inst = TmpInst;
7036 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7037 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7038 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7039 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7040 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7041 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7042 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7044 TmpInst.addOperand(Inst.getOperand(1)); // lane
7045 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7046 TmpInst.addOperand(Inst.getOperand(6));
7047 Inst = TmpInst;
7060 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7061 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7062 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7063 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7064 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7065 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7066 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7068 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7070 TmpInst.addOperand(Inst.getOperand(1)); // lane
7071 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7072 TmpInst.addOperand(Inst.getOperand(6));
7073 Inst = TmpInst;
7086 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7087 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7088 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7089 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7090 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7091 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7092 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7094 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7096 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7098 TmpInst.addOperand(Inst.getOperand(1)); // lane
7099 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7100 TmpInst.addOperand(Inst.getOperand(6));
7101 Inst = TmpInst;
7112 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7113 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7114 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7115 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7117 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7118 TmpInst.addOperand(Inst.getOperand(1)); // lane
7119 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7120 TmpInst.addOperand(Inst.getOperand(5));
7121 Inst = TmpInst;
7134 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7135 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7136 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7137 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7139 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7140 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7142 TmpInst.addOperand(Inst.getOperand(1)); // lane
7143 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7144 TmpInst.addOperand(Inst.getOperand(5));
7145 Inst = TmpInst;
7158 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7159 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7160 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7161 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7163 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7164 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7166 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7168 TmpInst.addOperand(Inst.getOperand(1)); // lane
7169 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7170 TmpInst.addOperand(Inst.getOperand(5));
7171 Inst = TmpInst;
7184 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7185 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7186 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7187 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7189 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7190 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7192 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7194 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7196 TmpInst.addOperand(Inst.getOperand(1)); // lane
7197 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7198 TmpInst.addOperand(Inst.getOperand(5));
7199 Inst = TmpInst;
7210 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7211 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7212 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7213 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7214 TmpInst.addOperand(Inst.getOperand(1)); // lane
7215 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7216 TmpInst.addOperand(Inst.getOperand(5));
7217 Inst = TmpInst;
7230 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7231 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7232 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7233 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7234 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7236 TmpInst.addOperand(Inst.getOperand(1)); // lane
7237 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7238 TmpInst.addOperand(Inst.getOperand(5));
7239 Inst = TmpInst;
7252 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7253 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7254 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7255 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7256 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7258 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7260 TmpInst.addOperand(Inst.getOperand(1)); // lane
7261 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7262 TmpInst.addOperand(Inst.getOperand(5));
7263 Inst = TmpInst;
7276 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7277 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7278 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7279 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7280 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7282 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7284 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7286 TmpInst.addOperand(Inst.getOperand(1)); // lane
7287 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7288 TmpInst.addOperand(Inst.getOperand(5));
7289 Inst = TmpInst;
7301 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7302 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7303 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7304 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7305 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7306 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7307 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7308 TmpInst.addOperand(Inst.getOperand(1)); // lane
7309 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7310 TmpInst.addOperand(Inst.getOperand(6));
7311 Inst = TmpInst;
7324 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7325 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7326 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7328 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7329 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7330 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7331 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7332 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7333 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7335 TmpInst.addOperand(Inst.getOperand(1)); // lane
7336 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7337 TmpInst.addOperand(Inst.getOperand(6));
7338 Inst = TmpInst;
7351 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7352 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7353 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7355 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7357 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7358 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7359 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7360 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7361 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7362 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7364 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7366 TmpInst.addOperand(Inst.getOperand(1)); // lane
7367 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7368 TmpInst.addOperand(Inst.getOperand(6));
7369 Inst = TmpInst;
7382 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7383 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7384 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7386 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7388 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7390 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7391 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7392 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7393 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7394 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7395 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7397 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7399 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7401 TmpInst.addOperand(Inst.getOperand(1)); // lane
7402 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7403 TmpInst.addOperand(Inst.getOperand(6));
7404 Inst = TmpInst;
7415 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7416 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7417 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7418 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7419 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7421 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7422 TmpInst.addOperand(Inst.getOperand(1)); // lane
7423 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7424 TmpInst.addOperand(Inst.getOperand(5));
7425 Inst = TmpInst;
7438 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7439 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7440 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7442 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7443 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7444 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7446 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7447 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7449 TmpInst.addOperand(Inst.getOperand(1)); // lane
7450 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7451 TmpInst.addOperand(Inst.getOperand(5));
7452 Inst = TmpInst;
7465 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7466 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7467 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7469 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7471 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7472 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7473 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7475 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7476 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7478 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7480 TmpInst.addOperand(Inst.getOperand(1)); // lane
7481 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7482 TmpInst.addOperand(Inst.getOperand(5));
7483 Inst = TmpInst;
7496 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7497 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7498 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7500 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7502 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7504 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7505 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7506 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7508 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7509 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7511 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7513 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7515 TmpInst.addOperand(Inst.getOperand(1)); // lane
7516 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7517 TmpInst.addOperand(Inst.getOperand(5));
7518 Inst = TmpInst;
7529 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7530 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7531 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7532 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7533 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7534 TmpInst.addOperand(Inst.getOperand(1)); // lane
7535 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7536 TmpInst.addOperand(Inst.getOperand(5));
7537 Inst = TmpInst;
7550 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7551 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7552 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7554 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7555 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7556 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7557 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7559 TmpInst.addOperand(Inst.getOperand(1)); // lane
7560 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7561 TmpInst.addOperand(Inst.getOperand(5));
7562 Inst = TmpInst;
7575 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7576 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7577 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7579 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7581 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7582 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7583 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7584 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7586 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7588 TmpInst.addOperand(Inst.getOperand(1)); // lane
7589 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7590 TmpInst.addOperand(Inst.getOperand(5));
7591 Inst = TmpInst;
7604 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7605 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7606 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7608 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7610 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7612 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7613 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7614 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7615 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7617 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7619 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7621 TmpInst.addOperand(Inst.getOperand(1)); // lane
7622 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7623 TmpInst.addOperand(Inst.getOperand(5));
7624 Inst = TmpInst;
7637 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7638 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7639 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7641 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7643 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7644 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7645 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7646 TmpInst.addOperand(Inst.getOperand(4));
7647 Inst = TmpInst;
7659 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7660 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7661 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7663 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7665 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7666 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7667 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7669 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7670 TmpInst.addOperand(Inst.getOperand(4));
7671 Inst = TmpInst;
7683 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7684 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7685 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7687 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7689 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7690 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7691 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7692 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7693 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7694 TmpInst.addOperand(Inst.getOperand(5));
7695 Inst = TmpInst;
7708 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7709 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7710 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7712 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7714 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7715 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7716 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7717 TmpInst.addOperand(Inst.getOperand(4));
7718 Inst = TmpInst;
7730 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7731 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7732 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7734 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7736 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7737 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7738 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7740 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7741 TmpInst.addOperand(Inst.getOperand(4));
7742 Inst = TmpInst;
7754 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7755 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7756 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7758 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7760 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7761 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7762 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7763 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7764 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7765 TmpInst.addOperand(Inst.getOperand(5));
7766 Inst = TmpInst;
7779 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7780 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7781 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7783 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7785 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7787 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7788 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7789 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7790 TmpInst.addOperand(Inst.getOperand(4));
7791 Inst = TmpInst;
7803 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7804 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7805 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7807 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7809 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7811 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7812 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7813 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7815 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7816 TmpInst.addOperand(Inst.getOperand(4));
7817 Inst = TmpInst;
7829 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7830 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7831 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7833 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7835 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7837 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7838 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7839 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7840 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7841 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7842 TmpInst.addOperand(Inst.getOperand(5));
7843 Inst = TmpInst;
7856 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7857 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7858 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7860 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7862 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7864 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7865 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7866 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7867 TmpInst.addOperand(Inst.getOperand(4));
7868 Inst = TmpInst;
7880 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7881 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7882 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7884 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7886 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7888 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7889 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7890 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7892 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7893 TmpInst.addOperand(Inst.getOperand(4));
7894 Inst = TmpInst;
7906 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7907 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7908 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7910 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7912 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7914 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7915 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7916 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7917 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7918 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7919 TmpInst.addOperand(Inst.getOperand(5));
7920 Inst = TmpInst;
7933 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7934 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7935 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7936 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7937 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7939 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7941 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7942 TmpInst.addOperand(Inst.getOperand(4));
7943 Inst = TmpInst;
7955 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7956 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7957 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7958 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7960 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7961 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7963 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7965 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7966 TmpInst.addOperand(Inst.getOperand(4));
7967 Inst = TmpInst;
7979 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7980 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7981 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7982 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7983 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7984 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7985 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7987 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7989 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7990 TmpInst.addOperand(Inst.getOperand(5));
7991 Inst = TmpInst;
8004 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8005 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8006 TmpInst.addOperand(Inst.getOperand(2)); // alignment
8007 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8008 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8010 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8012 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8014 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8015 TmpInst.addOperand(Inst.getOperand(4));
8016 Inst = TmpInst;
8028 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8029 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8030 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8031 TmpInst.addOperand(Inst.getOperand(2)); // alignment
8033 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8034 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8036 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8038 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8040 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8041 TmpInst.addOperand(Inst.getOperand(4));
8042 Inst = TmpInst;
8054 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8055 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8056 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
8057 TmpInst.addOperand(Inst.getOperand(2)); // alignment
8058 TmpInst.addOperand(Inst.getOperand(3)); // Rm
8059 TmpInst.addOperand(Inst.getOperand(0)); // Vd
8060 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8062 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8064 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
8066 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8067 TmpInst.addOperand(Inst.getOperand(5));
8068 Inst = TmpInst;
8076 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8077 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
8078 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
8082 switch (Inst.getOpcode()) {
8091 TmpInst.addOperand(Inst.getOperand(0));
8092 TmpInst.addOperand(Inst.getOperand(5));
8093 TmpInst.addOperand(Inst.getOperand(1));
8094 TmpInst.addOperand(Inst.getOperand(2));
8095 TmpInst.addOperand(Inst.getOperand(3));
8096 TmpInst.addOperand(Inst.getOperand(4));
8097 Inst = TmpInst;
8110 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8111 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8112 isARMLowRegister(Inst.getOperand(2).getReg()) &&
8113 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
8114 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
8118 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
8126 TmpInst.addOperand(Inst.getOperand(0)); // Rd
8129 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
8130 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8131 TmpInst.addOperand(Inst.getOperand(2)); // Rm
8132 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
8133 TmpInst.addOperand(Inst.getOperand(5));
8136 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
8137 Inst = TmpInst;
8146 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8147 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8148 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
8152 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
8160 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
8163 TmpInst.addOperand(Inst.getOperand(0)); // Rd
8166 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
8167 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8170 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8171 TmpInst.addOperand(Inst.getOperand(4));
8174 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
8175 Inst = TmpInst;
8184 switch(Inst.getOpcode()) {
8194 TmpInst.addOperand(Inst.getOperand(0)); // Rd
8195 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8196 TmpInst.addOperand(Inst.getOperand(2)); // Rm
8198 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8199 TmpInst.addOperand(Inst.getOperand(4));
8200 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
8201 Inst = TmpInst;
8209 switch(Inst.getOpcode()) {
8217 unsigned Amt = Inst.getOperand(2).getImm();
8225 TmpInst.addOperand(Inst.getOperand(0)); // Rd
8226 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8229 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8230 TmpInst.addOperand(Inst.getOperand(4));
8231 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
8232 Inst = TmpInst;
8239 TmpInst.addOperand(Inst.getOperand(0)); // Rd
8240 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8242 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8243 TmpInst.addOperand(Inst.getOperand(3));
8244 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
8245 Inst = TmpInst;
8251 if (Inst.getNumOperands() != 5)
8255 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8256 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8257 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8259 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8260 TmpInst.addOperand(Inst.getOperand(3));
8261 Inst = TmpInst;
8267 if (Inst.getNumOperands() != 5)
8271 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8272 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8273 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8275 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8276 TmpInst.addOperand(Inst.getOperand(3));
8277 Inst = TmpInst;
8284 Inst.getNumOperands() == 5) {
8287 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8288 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8289 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8292 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8293 TmpInst.addOperand(Inst.getOperand(3));
8294 Inst = TmpInst;
8302 Inst.getNumOperands() == 5) {
8305 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8306 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8307 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
8309 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8310 TmpInst.addOperand(Inst.getOperand(3));
8311 Inst = TmpInst;
8318 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
8320 Inst.setOpcode(ARM::t2ADDri);
8321 Inst.addOperand(MCOperand::createReg(0)); // cc_out
8327 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
8329 Inst.setOpcode(ARM::t2SUBri);
8330 Inst.addOperand(MCOperand::createReg(0)); // cc_out
8337 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
8338 Inst.setOpcode(ARM::tADDi3);
8347 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
8348 Inst.setOpcode(ARM::tSUBi3);
8358 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
8359 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
8360 (unsigned)Inst.getOperand(2).getImm() > 255 ||
8361 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
8362 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
8367 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
8369 TmpInst.addOperand(Inst.getOperand(0));
8370 TmpInst.addOperand(Inst.getOperand(5));
8371 TmpInst.addOperand(Inst.getOperand(0));
8372 TmpInst.addOperand(Inst.getOperand(2));
8373 TmpInst.addOperand(Inst.getOperand(3));
8374 TmpInst.addOperand(Inst.getOperand(4));
8375 Inst = TmpInst;
8385 auto DestReg = Inst.getOperand(0).getReg();
8386 bool Transform = DestReg == Inst.getOperand(1).getReg();
8387 if (!Transform && DestReg == Inst.getOperand(2).getReg()) {
8392 Inst.getOperand(5).getReg() != 0 ||
8398 TmpInst.addOperand(Inst.getOperand(0));
8399 TmpInst.addOperand(Inst.getOperand(0));
8400 TmpInst.addOperand(Inst.getOperand(Swap ? 1 : 2));
8401 TmpInst.addOperand(Inst.getOperand(3));
8402 TmpInst.addOperand(Inst.getOperand(4));
8403 Inst = TmpInst;
8409 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
8410 Inst.setOpcode(ARM::t2ADDrr);
8411 Inst.addOperand(MCOperand::createReg(0)); // cc_out
8418 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
8419 Inst.setOpcode(ARM::tBcc);
8425 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
8426 Inst.setOpcode(ARM::t2Bcc);
8432 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
8433 Inst.setOpcode(ARM::t2B);
8439 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
8440 Inst.setOpcode(ARM::tB);
8449 unsigned Rn = Inst.getOperand(0).getReg();
8454 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
8459 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
8463 Inst.insert(Inst.begin(),
8464 MCOperand::createReg(Inst.getOperand(0).getReg()));
8473 unsigned Rn = Inst.getOperand(0).getReg();
8475 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
8478 Inst.setOpcode(ARM::t2STMIA_UPD);
8488 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
8491 Inst.setOpcode(ARM::t2LDMIA_UPD);
8493 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8494 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8499 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
8502 Inst.setOpcode(ARM::t2STMDB_UPD);
8504 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8505 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8511 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8512 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
8513 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
8514 Inst.getOperand(4).getReg() == ARM::CPSR) ||
8515 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
8521 TmpInst.addOperand(Inst.getOperand(0));
8522 TmpInst.addOperand(Inst.getOperand(4));
8523 TmpInst.addOperand(Inst.getOperand(1));
8524 TmpInst.addOperand(Inst.getOperand(2));
8525 TmpInst.addOperand(Inst.getOperand(3));
8526 Inst = TmpInst;
8534 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8535 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8536 Inst.getOperand(2).getImm() == ARMCC::AL &&
8537 Inst.getOperand(4).getReg() == ARM::CPSR &&
8542 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
8543 TmpInst.addOperand(Inst.getOperand(0));
8544 TmpInst.addOperand(Inst.getOperand(1));
8545 TmpInst.addOperand(Inst.getOperand(2));
8546 TmpInst.addOperand(Inst.getOperand(3));
8547 Inst = TmpInst;
8558 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8559 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8560 Inst.getOperand(2).getImm() == 0 &&
8564 switch (Inst.getOpcode()) {
8574 TmpInst.addOperand(Inst.getOperand(0));
8575 TmpInst.addOperand(Inst.getOperand(1));
8576 TmpInst.addOperand(Inst.getOperand(3));
8577 TmpInst.addOperand(Inst.getOperand(4));
8578 Inst = TmpInst;
8584 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
8588 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
8592 TmpInst.addOperand(Inst.getOperand(0));
8593 TmpInst.addOperand(Inst.getOperand(1));
8594 TmpInst.addOperand(Inst.getOperand(3));
8595 TmpInst.addOperand(Inst.getOperand(4));
8596 TmpInst.addOperand(Inst.getOperand(5));
8597 Inst = TmpInst;
8609 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
8611 switch (Inst.getOpcode()) {
8622 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
8626 TmpInst.addOperand(Inst.getOperand(0));
8627 TmpInst.addOperand(Inst.getOperand(1));
8628 TmpInst.addOperand(Inst.getOperand(2));
8629 TmpInst.addOperand(Inst.getOperand(4));
8630 TmpInst.addOperand(Inst.getOperand(5));
8631 TmpInst.addOperand(Inst.getOperand(6));
8632 Inst = TmpInst;
8643 MCOperand &MO = Inst.getOperand(1);
8647 if ((Inst.getOperand(0).getImm() & 1) == 0) {
8656 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
8670 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8671 isARMLowRegister(Inst.getOperand(2).getReg())) &&
8672 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
8673 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8674 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8679 switch (Inst.getOpcode()) {
8690 TmpInst.addOperand(Inst.getOperand(0));
8691 TmpInst.addOperand(Inst.getOperand(5));
8692 TmpInst.addOperand(Inst.getOperand(1));
8693 TmpInst.addOperand(Inst.getOperand(2));
8694 TmpInst.addOperand(Inst.getOperand(3));
8695 TmpInst.addOperand(Inst.getOperand(4));
8696 Inst = TmpInst;
8709 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8710 isARMLowRegister(Inst.getOperand(2).getReg())) &&
8711 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
8712 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
8713 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8714 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8719 switch (Inst.getOpcode()) {
8728 TmpInst.addOperand(Inst.getOperand(0));
8729 TmpInst.addOperand(Inst.getOperand(5));
8730 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
8731 TmpInst.addOperand(Inst.getOperand(1));
8732 TmpInst.addOperand(Inst.getOperand(2));
8734 TmpInst.addOperand(Inst.getOperand(2));
8735 TmpInst.addOperand(Inst.getOperand(1));
8737 TmpInst.addOperand(Inst.getOperand(3));
8738 TmpInst.addOperand(Inst.getOperand(4));
8739 Inst = TmpInst;
8748 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
8751 unsigned Opc = Inst.getOpcode();
8756 assert(MCID.NumOperands == Inst.getNumOperands() &&
8765 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
8769 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
8772 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
8779 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8780 isARMLowRegister(Inst.getOperand(2).getReg()))
8784 isARMLowRegister(Inst.getOperand(0).getReg()) &&
8785 isARMLowRegister(Inst.getOperand(1).getReg()))
8792 if ((Inst.getOperand(I).getReg() == ARM::SP) && !hasV8Ops())
8794 else if (Inst.getOperand(I).getReg() == ARM::PC)
8812 MCInst Inst;
8815 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
8821 if (validateInstruction(Inst, Operands)) {
8835 while (processInstruction(Inst, Operands, Out))
8840 !isV8EligibleForIT(&Inst)) {
8852 if (Inst.getOpcode() == ARM::ITasm)
8855 Inst.setLoc(IDLoc);
8856 Out.EmitInstruction(Inst, getSTI());