Cross Reference: /external/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp

Lines Matching refs:Sub
360 // For a register ref (pair Reg:Sub), set Begin to the position of the LSB
361 // of Sub in Reg, and set Width to the size of Sub in bits. Return true,
367     assert(RR.Sub == 0);
373     if (RR.Sub == 0) {
378     assert(RR.Sub == Hexagon::subreg_loreg || RR.Sub == Hexagon::subreg_hireg);
380     Begin = (RR.Sub == Hexagon::subreg_loreg ? 0 : 32);
846 // Calculate the register class that matches Reg:Sub. For example, if
854   if (RR.Sub == 0)
857   auto VerifySR = [] (unsigned Sub) -> void {
858     assert(Sub == Hexagon::subreg_hireg || Sub == Hexagon::subreg_loreg);
863       VerifySR(RR.Sub);
866       VerifySR(RR.Sub);
869       VerifySR(RR.Sub);
1296           .addReg(RS.Reg, 0, RS.Sub);
1297       HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI);
1488 /// set Out to the found register. The output may be a pair Reg:Sub.
1509       Out.Sub = 0;
1521       Out.Sub = Hexagon::subreg_loreg;
1523       Out.Sub = Hexagon::subreg_hireg;
1558         .addReg(MR.Reg, 0, MR.Sub);
1597       if (RS.Sub != 0)
1598         Changed = HBS::replaceRegWithSub(RD.Reg, RS.Reg, RS.Sub, MRI);
1607                                          SL.Reg, SL.Sub, MRI);
1609                                           SH.Reg, SH.Sub, MRI);
1616                                        RL.Reg, RL.Sub, MRI);
1618                                         RH.Reg, RH.Sub, MRI);
1624       unsigned Sub = (Opc == Hexagon::A4_combineir) ? Hexagon::subreg_loreg
1627       Changed = HBS::replaceSubWithSub(RD.Reg, Sub, RS.Reg, RS.Sub, MRI);
1746   unsigned Sub = 0;
1749       Sub = Hexagon::subreg_loreg;
1753       Sub = Hexagon::subreg_loreg;
1757       Sub = Hexagon::subreg_hireg;
1761       Sub = Hexagon::subreg_hireg;
1769   RH.Sub = Sub;
1773     RH.Sub = 0;
1792   if (H1.Reg != L1.Reg || H1.Sub != L1.Sub || H1.Low || !L1.Low)
1794   if (H2.Reg != L2.Reg || H2.Sub != L2.Sub || H2.Low || !L2.Low)
1831   ValOp.setSubReg(H.Sub);
1924       .addReg(Rs.Reg, 0, Rs.Sub)
1925       .addReg(Rt.Reg, 0, Rt.Sub);
1926   HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI);
1953         .addReg(L.Reg, 0, L.Sub);
1957         .addReg(L.Reg, 0, L.Sub)
1962   HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI);
1977   if (L.Reg == H.Reg && L.Sub == H.Sub && !H.Low && L.Low)
1991       .addReg(H.Reg, 0, H.Sub)
1992       .addReg(L.Reg, 0, L.Sub);
1993   HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI);
2047                   .addReg(RS.Reg, 0, RS.Sub);
2052     HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI);
2093       RR.Sub = Hexagon::subreg_loreg;
2096         RR.Sub = Hexagon::subreg_hireg;
2104           .addReg(RR.Reg, 0, RR.Sub)
2554              << PrintReg(I.PR.Reg, HRI, I.PR.Sub) << ":b" << I.PB->getNumber()
2555              << ',' << PrintReg(I.LR.Reg, HRI, I.LR.Sub) << ":b"
2675              << PrintReg(G.Inp.Reg, HRI, G.Inp.Sub)
2676              << "  out: " << PrintReg(G.Out.Reg, HRI, G.Out.Sub) << "\n";