Cross Reference: /external/llvm/lib/Target/Mips/MipsISelLowering.cpp

Lines Matching refs:RC
931 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
933   unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
1110   const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1146   unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1147   unsigned AndRes = RegInfo.createVirtualRegister(RC);
1148   unsigned Success = RegInfo.createVirtualRegister(RC);
1214   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1215   unsigned ScrReg = RegInfo.createVirtualRegister(RC);
1234   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1246   unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1247   unsigned Mask = RegInfo.createVirtualRegister(RC);
1248   unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1249   unsigned NewVal = RegInfo.createVirtualRegister(RC);
1250   unsigned OldVal = RegInfo.createVirtualRegister(RC);
1251   unsigned Incr2 = RegInfo.createVirtualRegister(RC);
1253   unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1254   unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1255   unsigned AndRes = RegInfo.createVirtualRegister(RC);
1256   unsigned BinOpRes = RegInfo.createVirtualRegister(RC);
1257   unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1258   unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1259   unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1260   unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1261   unsigned Success = RegInfo.createVirtualRegister(RC);
1314     unsigned Off = RegInfo.createVirtualRegister(RC);
1398   const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1433   unsigned Success = RegInfo.createVirtualRegister(RC);
1488   const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1501   unsigned ShiftAmt = RegInfo.createVirtualRegister(RC);
1502   unsigned Mask = RegInfo.createVirtualRegister(RC);
1503   unsigned Mask2 = RegInfo.createVirtualRegister(RC);
1504   unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC);
1505   unsigned OldVal = RegInfo.createVirtualRegister(RC);
1506   unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC);
1507   unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC);
1509   unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC);
1510   unsigned MaskUpper = RegInfo.createVirtualRegister(RC);
1511   unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC);
1512   unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC);
1513   unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC);
1514   unsigned StoreVal = RegInfo.createVirtualRegister(RC);
1515   unsigned SrlRes = RegInfo.createVirtualRegister(RC);
1516   unsigned Success = RegInfo.createVirtualRegister(RC);
1577     unsigned Off = RegInfo.createVirtualRegister(RC);
3082       const TargetRegisterClass *RC = getRegClassFor(RegVT);
3086       unsigned Reg = addLiveIn(DAG.getMachineFunction(), ArgReg, RC);
3100                                   getNextIntArgReg(ArgReg), RC);
3432   const TargetRegisterClass *RC;
3446     RC = TRI->getRegClass(Prefix == "hi" ?
3448     return std::make_pair(*(RC->begin()), RC);
3470     RC = TRI->getRegClass(Mips::MSACtrlRegClassID);
3471     return std::make_pair(Reg, RC);
3483     RC = getRegClassFor(VT);
3485     if (RC == &Mips::AFGR64RegClass) {
3490     RC = TRI->getRegClass(Mips::FCCRegClassID);
3492     RC = getRegClassFor((VT == MVT::Other) ? MVT::v16i8 : VT);
3495     RC = getRegClassFor((VT == MVT::Other) ? MVT::i32 : VT);
3498   assert(Reg < RC->getNumRegs());
3499   return std::make_pair(*(RC->begin() + Reg), RC);
3753   const TargetRegisterClass *RC = getRegClassFor(RegTy);
3757     unsigned VReg = addLiveIn(MF, ArgReg, RC);
3875   const TargetRegisterClass *RC = getRegClassFor(RegTy);
3902     unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);