Cross Reference: /external/mesa3d/src/gallium/drivers/r600/r600

Lines Matching refs:surface
64 	return rtex->surface.level[level].offset +
65 	       layer * rtex->surface.level[level].slice_size;
69 			     struct radeon_surface *surface,
81 	surface->npix_x = ptex->width0;
82 	surface->npix_y = ptex->height0;
83 	surface->npix_z = ptex->depth0;
84 	surface->blk_w = util_format_get_blockwidth(ptex->format);
85 	surface->blk_h = util_format_get_blockheight(ptex->format);
86 	surface->blk_d = 1;
87 	surface->array_size = 1;
88 	surface->last_level = ptex->last_level;
93 		surface->bpe = 4; /* stencil is allocated separately on evergreen */
95 		surface->bpe = util_format_get_blocksize(ptex->format);
97 		if (surface->bpe == 3) {
98 			surface->bpe = 4;
102 	surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
103 	surface->flags = 0;
107 		surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
110 		surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
113 		surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
117 		surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
122 		surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
126 		surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
129 		surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
132 		surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
133 		surface->array_size = ptex->array_size;
136 		surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
137 		surface->array_size = ptex->array_size;
140 		surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
147 		surface->flags |= RADEON_SURF_SCANOUT;
151 		surface->flags |= RADEON_SURF_ZBUFFER;
154 			surface->flags |= RADEON_SURF_SBUFFER;
169 	r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
173 	rtex->size = rtex->surface.bo_size;
174 	if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
178 		rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
179 		rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
180 		rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
181 		if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
182 			rtex->surface.stencil_offset = rtex->surface.level[0].slice_size;
186 		switch (rtex->surface.level[i].mode) {
211 	struct radeon_surface *surface = &rtex->surface;
216 				       surface->level[0].mode >= RADEON_SURF_MODE_1D ?
218 				       surface->level[0].mode >= RADEON_SURF_MODE_2D ?
220 				       surface->bankw, surface->bankh,
221 				       surface->tile_split,
222 				       surface->stencil_tile_split,
223 				       surface->mtilea,
224 				       rtex->surface.level[0].pitch_bytes);
227 					      rtex->surface.level[0].pitch_bytes, whandle);
263 	struct radeon_surface fmask = rtex->surface;
268 		 * for the allocator to treat it as a multisample surface.
344 	unsigned pitch_elements = align(rtex->surface.npix_x, macro_tile_width);
345 	unsigned height = align(rtex->surface.npix_y, macro_tile_height);
356 	out->size = rtex->surface.array_size * align(slice_bytes, base_align);
384 			   struct radeon_surface *surface)
405 	rtex->surface = *surface;
426 		unsigned base_align = rtex->surface.bo_alignment;
452 	struct radeon_surface surface;
472 	r = r600_init_surface(rscreen, &surface, templ, array_mode,
478 	r = rscreen->ws->surface_best(rscreen->ws, &surface);
483 								  0, NULL, TRUE, &surface);
491 	struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
495 	if (surface == NULL)
497 	pipe_reference_init(&surface->base.reference, 1);
498 	pipe_resource_reference(&surface->base.texture, texture);
499 	surface->base.context = pipe;
500 	surface->base.format = templ->format;
501 	surface->base.width = rtex->surface.level[level].npix_x;
502 	surface->base.height = rtex->surface.level[level].npix_y;
503 	surface->base.usage = templ->usage;
504 	surface->base.u = templ->u;
505 	return &surface->base;
509 				 struct pipe_surface *surface)
511 	struct r600_surface *surf = (struct r600_surface*)surface;
514 	pipe_resource_reference(&surface->texture, NULL);
515 	FREE(surface);
527 	struct radeon_surface surface;
540 				       &surface.bankw, &surface.bankh,
541 				       &surface.tile_split,
542 				       &surface.stencil_tile_split,
543 				       &surface.mtilea);
552 	r = r600_init_surface(rscreen, &surface, templ, array_mode, false, false);
557 								  stride, buf, FALSE, &surface);
661 		trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes;
697 			((struct r600_texture *)trans->staging)->surface.level[0].pitch_bytes;
705 	trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
706 	trans->transfer.layer_stride = rtex->surface.level[level].slice_size;