Cross Reference: /external/mesa3d/src/gallium/drivers/radeonsi/r600

Lines Matching refs:surface
72 	return rtex->surface.level[level].offset +
73 	       layer * rtex->surface.level[level].slice_size;
76 static int r600_init_surface(struct radeon_surface *surface,
80 	surface->npix_x = ptex->width0;
81 	surface->npix_y = ptex->height0;
82 	surface->npix_z = ptex->depth0;
83 	surface->blk_w = util_format_get_blockwidth(ptex->format);
84 	surface->blk_h = util_format_get_blockheight(ptex->format);
85 	surface->blk_d = 1;
86 	surface->array_size = 1;
87 	surface->last_level = ptex->last_level;
88 	surface->bpe = util_format_get_blocksize(ptex->format);
90 	if (surface->bpe == 3) {
91 		surface->bpe = 4;
93 	surface->nsamples = 1;
94 	surface->flags = 0;
97 		surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
100 		surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
103 		surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
107 		surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE);
112 		surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
116 		surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
119 		surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
122 		surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
123 		surface->array_size = ptex->array_size;
126 		surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
127 		surface->array_size = ptex->array_size;
130 		surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
137 		surface->flags |= RADEON_SURF_SCANOUT;
140 		surface->flags |= RADEON_SURF_ZBUFFER;
141 		surface->flags |= RADEON_SURF_SBUFFER;
156 		rtex->surface.flags |= RADEON_SURF_ZBUFFER;
157 		rtex->surface.flags |= RADEON_SURF_SBUFFER;
160 	r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface);
164 	if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
168 		rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe;
169 		rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
170 		rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y;
171 		if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
172 			rtex->surface.stencil_offset = rtex->surface.level[0].slice_size;
225 	struct radeon_surface *surface = &rtex->surface;
230 				       surface->level[0].mode >= RADEON_SURF_MODE_1D ?
232 				       surface->level[0].mode >= RADEON_SURF_MODE_2D ?
234 				       surface->bankw, surface->bankh,
235 				       surface->tile_split,
236 				       surface->stencil_tile_split,
237 				       surface->mtilea,
238 				       surface->level[0].pitch_bytes);
241 					      surface->level[0].pitch_bytes, whandle);
283 	if (rtex->surface.level[level].mode != RADEON_SURF_MODE_LINEAR_ALIGNED &&
284 	    rtex->surface.level[level].mode != RADEON_SURF_MODE_LINEAR)
327 		trans->transfer.stride = rtex->flushed_depth_texture->surface.level[level].pitch_bytes;
362 					->surface.level[0].pitch_bytes;
370 	trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
371 	trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
472 			   struct radeon_surface *surface)
495 	rtex->surface = *surface;
504 		unsigned base_align = rtex->surface.bo_alignment;
505 		unsigned size = rtex->surface.bo_size;
507 		base_align = rtex->surface.bo_alignment;
525 	struct radeon_surface surface;
538 	r = r600_init_surface(&surface, templ, array_mode);
542 	r = rscreen->ws->surface_best(rscreen->ws, &surface);
547 								  0, 0, NULL, TRUE, &surface);
555 	struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
559 	if (surface == NULL)
563 	pipe_reference_init(&surface->base.reference, 1);
564 	pipe_resource_reference(&surface->base.texture, texture);
565 	surface->base.context = pipe;
566 	surface->base.format = surf_tmpl->format;
567 	surface->base.width = rtex->surface.level[level].npix_x;
568 	surface->base.height = rtex->surface.level[level].npix_y;
569 	surface->base.usage = surf_tmpl->usage;
570 	surface->base.texture = texture;
571 	surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
572 	surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
573 	surface->base.u.tex.level = level;
575 	return &surface->base;
579 				 struct pipe_surface *surface)
581 	pipe_resource_reference(&surface->texture, NULL);
582 	FREE(surface);
594 	struct radeon_surface surface;
607 				       &surface.bankw, &surface.bankh,
608 				       &surface.tile_split,
609 				       &surface.stencil_tile_split,
610 				       &surface.mtilea);
619 	r = r600_init_surface(&surface, templ, array_mode);
624 								  stride, 0, buf, FALSE, &surface);