Cross Reference: /external/mesa3d/src/mesa/drivers/dri/radeon/radeon

Lines Matching refs:radeon
94 static void r100_get_lock(radeonContextPtr radeon)
96    r100ContextPtr rmesa = (r100ContextPtr)radeon;
97    drm_radeon_sarea_t *sarea = radeon->sarea;
100    if (rmesa->radeon.sarea->tiling_enabled) {
108    if (sarea->ctx_owner != rmesa->radeon.dri.hwContext) {
109       sarea->ctx_owner = rmesa->radeon.dri.hwContext;
117 static void r100_vtbl_pre_emit_state(radeonContextPtr radeon)
119    r100ContextPtr rmesa = (r100ContextPtr)radeon;
123    radeon->hw.is_dirty = 1;
132 static void r100_emit_query_finish(radeonContextPtr radeon)
134    BATCH_LOCALS(radeon);
135    struct radeon_query_object *query = radeon->query.current;
146 static void r100_init_vtbl(radeonContextPtr radeon)
148    radeon->vtbl.get_lock = r100_get_lock;
149    radeon->vtbl.update_viewport_offset = radeonUpdateViewportOffset;
150    radeon->vtbl.emit_cs_header = r100_vtbl_emit_cs_header;
151    radeon->vtbl.swtcl_flush = r100_swtcl_flush;
152    radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state;
153    radeon->vtbl.fallback = radeonFallback;
154    radeon->vtbl.free_context = r100_vtbl_free_context;
155    radeon->vtbl.emit_query_finish = r100_emit_query_finish;
156    radeon->vtbl.check_blit = r100_check_blit;
157    radeon->vtbl.blit = r100_blit;
158    radeon->vtbl.is_format_renderable = radeonIsFormatRenderable;
210    rmesa->radeon.radeonScreen = screen;
211    r100_init_vtbl(&rmesa->radeon);
220    driParseConfigFiles (&rmesa->radeon.optionCache, &screen->optionCache,
221 			screen->driScreen->myNum, "radeon");
222    rmesa->radeon.initialMaxAnisotropy = driQueryOptionf(&rmesa->radeon.optionCache,
225    if ( driQueryOptionb( &rmesa->radeon.optionCache, "hyperz" ) ) {
240    radeonInitTextureFuncs( &rmesa->radeon, &functions );
243    if (!radeonInitContext(&rmesa->radeon, &functions,
251    rmesa->radeon.swtcl.RenderIndex = ~0;
252    rmesa->radeon.hw.all_dirty = GL_TRUE;
254    ctx = rmesa->radeon.glCtx;
269    ctx->Const.MaxTextureUnits = driQueryOptioni (&rmesa->radeon.optionCache,
277    i = driQueryOptioni( &rmesa->radeon.optionCache, "allow_large_textures");
364    if (rmesa->radeon.glCtx->Mesa_DXTn) {
368    else if (driQueryOptionb (&rmesa->radeon.optionCache, "force_s3tc_enable")) {
376    radeon_fbo_init(&rmesa->radeon);
386    fthrottle_mode = driQueryOptioni(&rmesa->radeon.optionCache, "fthrottle_mode");
387    rmesa->radeon.iw.irq_seq = -1;
388    rmesa->radeon.irqsEmitted = 0;
389    rmesa->radeon.do_irqs = (rmesa->radeon.radeonScreen->irq != 0 &&
392    rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
400    tcl_mode = driQueryOptioni(&rmesa->radeon.optionCache, "tcl_mode");
401    if (driQueryOptionb(&rmesa->radeon.optionCache, "no_rast")) {
405 	      !(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
406       if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
407 	 rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
410       TCL_FALLBACK(rmesa->radeon.glCtx, RADEON_TCL_FALLBACK_TCL_DISABLE, 1);
413    if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {