Lines Matching refs:ExtVT
2430 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
2433 if (ExtVT == LoadedVT &&
2434 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2441 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
2451 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
2452 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
2463 unsigned EVTStoreBytes = ExtVT.getStoreSize();
2477 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
3394 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits);
3396 ExtVT = EVT::getVectorVT(*DAG.getContext(),
3397 ExtVT, VT.getVectorNumElements());
3399 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT)))
3401 N0.getOperand(0), DAG.getValueType(ExtVT));
4609 EVT ExtVT = VT;
4615 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then
4619 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
4626 ExtVT = EVT::getIntegerVT(*DAG.getContext(),
4629 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
4632 unsigned EVTBits = ExtVT.getSizeInBits();
4636 if (!ExtVT.isRound())
4668 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
4693 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
4712 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(),
6854 EVT ExtVT = VT.getVectorElementType();
6855 EVT LVT = ExtVT;
6859 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
6864 ExtVT = BCVT.getVectorElementType();
6873 InVec.getOperand(0).getValueType() == ExtVT &&