Lines Matching defs:AR5K_EEPROM_N_MODES
179 #define AR5K_EEPROM_N_MODES 3
394 u16 ee_i_cal[AR5K_EEPROM_N_MODES];
395 u16 ee_q_cal[AR5K_EEPROM_N_MODES];
396 u16 ee_fixed_bias[AR5K_EEPROM_N_MODES];
397 u16 ee_turbo_max_power[AR5K_EEPROM_N_MODES];
398 u16 ee_xr_power[AR5K_EEPROM_N_MODES];
399 u16 ee_switch_settling[AR5K_EEPROM_N_MODES];
400 u16 ee_atn_tx_rx[AR5K_EEPROM_N_MODES];
401 u16 ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC];
402 u16 ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
403 u16 ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
404 u16 ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES];
405 u16 ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES];
406 u16 ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES];
407 u16 ee_thr_62[AR5K_EEPROM_N_MODES];
408 u16 ee_xlna_gain[AR5K_EEPROM_N_MODES];
409 u16 ee_xpd[AR5K_EEPROM_N_MODES];
410 u16 ee_x_gain[AR5K_EEPROM_N_MODES];
411 u16 ee_i_gain[AR5K_EEPROM_N_MODES];
412 u16 ee_margin_tx_rx[AR5K_EEPROM_N_MODES];
413 u16 ee_switch_settling_turbo[AR5K_EEPROM_N_MODES];
414 u16 ee_margin_tx_rx_turbo[AR5K_EEPROM_N_MODES];
415 u16 ee_atn_tx_rx_turbo[AR5K_EEPROM_N_MODES];
418 u16 ee_false_detect[AR5K_EEPROM_N_MODES];
421 u8 ee_pd_gains[AR5K_EEPROM_N_MODES];
423 u8 ee_pdc_to_idx[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PD_GAINS];
425 u8 ee_n_piers[AR5K_EEPROM_N_MODES];
431 u8 ee_rate_target_pwr_num[AR5K_EEPROM_N_MODES];
442 s16 ee_noise_floor_thr[AR5K_EEPROM_N_MODES];
443 s8 ee_adc_desired_size[AR5K_EEPROM_N_MODES];
444 s8 ee_pga_desired_size[AR5K_EEPROM_N_MODES];
445 s8 ee_adc_desired_size_turbo[AR5K_EEPROM_N_MODES];
446 s8 ee_pga_desired_size_turbo[AR5K_EEPROM_N_MODES];
449 u32 ee_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];