Lines Matching refs:Ain
592 i->Ain.Imm64.imm64 = imm64;
593 i->Ain.Imm64.dst = dst;
599 i->Ain.Alu64R.op = op;
600 i->Ain.Alu64R.src = src;
601 i->Ain.Alu64R.dst = dst;
607 i->Ain.Alu64M.op = op;
608 i->Ain.Alu64M.src = src;
609 i->Ain.Alu64M.dst = dst;
616 i->Ain.Sh64.op = op;
617 i->Ain.Sh64.src = src;
618 i->Ain.Sh64.dst = dst;
624 i->Ain.Test64.imm32 = imm32;
625 i->Ain.Test64.dst = dst;
631 i->Ain.Unary64.op = op;
632 i->Ain.Unary64.dst = dst;
638 i->Ain.Lea64.am = am;
639 i->Ain.Lea64.dst = dst;
645 i->Ain.Alu32R.op = op;
646 i->Ain.Alu32R.src = src;
647 i->Ain.Alu32R.dst = dst;
658 i->Ain.MulL.syned = syned;
659 i->Ain.MulL.src = src;
665 i->Ain.Div.syned = syned;
666 i->Ain.Div.sz = sz;
667 i->Ain.Div.src = src;
674 i->Ain.Push.src = src;
681 i->Ain.Call.cond = cond;
682 i->Ain.Call.target = target;
683 i->Ain.Call.regparms = regparms;
684 i->Ain.Call.rloc = rloc;
694 i->Ain.XDirect.dstGA = dstGA;
695 i->Ain.XDirect.amRIP = amRIP;
696 i->Ain.XDirect.cond = cond;
697 i->Ain.XDirect.toFastEP = toFastEP;
704 i->Ain.XIndir.dstGA = dstGA;
705 i->Ain.XIndir.amRIP = amRIP;
706 i->Ain.XIndir.cond = cond;
713 i->Ain.XAssisted.dstGA = dstGA;
714 i->Ain.XAssisted.amRIP = amRIP;
715 i->Ain.XAssisted.cond = cond;
716 i->Ain.XAssisted.jk = jk;
723 i->Ain.CMov64.cond = cond;
724 i->Ain.CMov64.src = src;
725 i->Ain.CMov64.dst = dst;
733 i->Ain.CLoad.cond = cond;
734 i->Ain.CLoad.szB = szB;
735 i->Ain.CLoad.addr = addr;
736 i->Ain.CLoad.dst = dst;
744 i->Ain.CStore.cond = cond;
745 i->Ain.CStore.szB = szB;
746 i->Ain.CStore.src = src;
747 i->Ain.CStore.addr = addr;
754 i->Ain.MovxLQ.syned = syned;
755 i->Ain.MovxLQ.src = src;
756 i->Ain.MovxLQ.dst = dst;
763 i->Ain.LoadEX.szSmall = szSmall;
764 i->Ain.LoadEX.syned = syned;
765 i->Ain.LoadEX.src = src;
766 i->Ain.LoadEX.dst = dst;
773 i->Ain.Store.sz = sz;
774 i->Ain.Store.src = src;
775 i->Ain.Store.dst = dst;
782 i->Ain.Set64.cond = cond;
783 i->Ain.Set64.dst = dst;
789 i->Ain.Bsfr64.isFwds = isFwds;
790 i->Ain.Bsfr64.src = src;
791 i->Ain.Bsfr64.dst = dst;
802 i->Ain.ACAS.addr = addr;
803 i->Ain.ACAS.sz = sz;
810 i->Ain.DACAS.addr = addr;
811 i->Ain.DACAS.sz = sz;
820 i->Ain.A87Free.nregs = nregs;
828 i->Ain.A87PushPop.addr = addr;
829 i->Ain.A87PushPop.isPush = isPush;
830 i->Ain.A87PushPop.szB = szB;
838 i->Ain.A87FpOp.op = op;
845 i->Ain.A87LdCW.addr = addr;
852 i->Ain.A87StSW.addr = addr;
858 i->Ain.LdMXCSR.addr = addr;
864 i->Ain.SseUComIS.sz = toUChar(sz);
865 i->Ain.SseUComIS.srcL = srcL;
866 i->Ain.SseUComIS.srcR = srcR;
867 i->Ain.SseUComIS.dst = dst;
874 i->Ain.SseSI2SF.szS = toUChar(szS);
875 i->Ain.SseSI2SF.szD = toUChar(szD);
876 i->Ain.SseSI2SF.src = src;
877 i->Ain.SseSI2SF.dst = dst;
885 i->Ain.SseSF2SI.szS = toUChar(szS);
886 i->Ain.SseSF2SI.szD = toUChar(szD);
887 i->Ain.SseSF2SI.src = src;
888 i->Ain.SseSF2SI.dst = dst;
897 i->Ain.SseSDSS.from64 = from64;
898 i->Ain.SseSDSS.src = src;
899 i->Ain.SseSDSS.dst = dst;
906 i->Ain.SseLdSt.isLoad = isLoad;
907 i->Ain.SseLdSt.sz = toUChar(sz);
908 i->Ain.SseLdSt.reg = reg;
909 i->Ain.SseLdSt.addr = addr;
918 i->Ain.SseCStore.cond = cond;
919 i->Ain.SseCStore.src = src;
920 i->Ain.SseCStore.addr = addr;
929 i->Ain.SseCLoad.cond = cond;
930 i->Ain.SseCLoad.addr = addr;
931 i->Ain.SseCLoad.dst = dst;
939 i->Ain.SseLdzLO.sz = sz;
940 i->Ain.SseLdzLO.reg = reg;
941 i->Ain.SseLdzLO.addr = addr;
948 i->Ain.Sse32Fx4.op = op;
949 i->Ain.Sse32Fx4.src = src;
950 i->Ain.Sse32Fx4.dst = dst;
957 i->Ain.Sse32FLo.op = op;
958 i->Ain.Sse32FLo.src = src;
959 i->Ain.Sse32FLo.dst = dst;
966 i->Ain.Sse64Fx2.op = op;
967 i->Ain.Sse64Fx2.src = src;
968 i->Ain.Sse64Fx2.dst = dst;
975 i->Ain.Sse64FLo.op = op;
976 i->Ain.Sse64FLo.src = src;
977 i->Ain.Sse64FLo.dst = dst;
984 i->Ain.SseReRg.op = op;
985 i->Ain.SseReRg.src = re;
986 i->Ain.SseReRg.dst = rg;
992 i->Ain.SseCMov.cond = cond;
993 i->Ain.SseCMov.src = src;
994 i->Ain.SseCMov.dst = dst;
1001 i->Ain.SseShuf.order = order;
1002 i->Ain.SseShuf.src = src;
1003 i->Ain.SseShuf.dst = dst;
1011 //uu i->Ain.AvxLdSt.isLoad = isLoad;
1012 //uu i->Ain.AvxLdSt.reg = reg;
1013 //uu i->Ain.AvxLdSt.addr = addr;
1019 //uu i->Ain.AvxReRg.op = op;
1020 //uu i->Ain.AvxReRg.src = re;
1021 //uu i->Ain.AvxReRg.dst = rg;
1028 i->Ain.EvCheck.amCounter = amCounter;
1029 i->Ain.EvCheck.amFailAddr = amFailAddr;
1043 vex_printf("movabsq $0x%llx,", i->Ain.Imm64.imm64);
1044 ppHRegAMD64(i->Ain.Imm64.dst);
1047 vex_printf("%sq ", showAMD64AluOp(i->Ain.Alu64R.op));
1048 ppAMD64RMI(i->Ain.Alu64R.src);
1050 ppHRegAMD64(i->Ain.Alu64R.dst);
1053 vex_printf("%sq ", showAMD64AluOp(i->Ain.Alu64M.op));
1054 ppAMD64RI(i->Ain.Alu64M.src);
1056 ppAMD64AMode(i->Ain.Alu64M.dst);
1059 vex_printf("%sq ", showAMD64ShiftOp(i->Ain.Sh64.op));
1060 if (i->Ain.Sh64.src == 0)
1063 vex_printf("$%d,", (Int)i->Ain.Sh64.src);
1064 ppHRegAMD64(i->Ain.Sh64.dst);
1067 vex_printf("testq $%d,", (Int)i->Ain.Test64.imm32);
1068 ppHRegAMD64(i->Ain.Test64.dst);
1071 vex_printf("%sq ", showAMD64UnaryOp(i->Ain.Unary64.op));
1072 ppHRegAMD64(i->Ain.Unary64.dst);
1076 ppAMD64AMode(i->Ain.Lea64.am);
1078 ppHRegAMD64(i->Ain.Lea64.dst);
1081 vex_printf("%sl ", showAMD64AluOp(i->Ain.Alu32R.op));
1082 ppAMD64RMI_lo32(i->Ain.Alu32R.src);
1084 ppHRegAMD64_lo32(i->Ain.Alu32R.dst);
1087 vex_printf("%cmulq ", i->Ain.MulL.syned ? 's' : 'u');
1088 ppAMD64RM(i->Ain.MulL.src);
1092 i->Ain.Div.syned ? 's' : 'u',
1093 showAMD64ScalarSz(i->Ain.Div.sz));
1094 ppAMD64RM(i->Ain.Div.src);
1098 ppAMD64RMI(i->Ain.Push.src);
1102 i->Ain.Call.cond==Acc_ALWAYS
1103 ? "" : showAMD64CondCode(i->Ain.Call.cond),
1104 i->Ain.Call.regparms );
1105 ppRetLoc(i->Ain.Call.rloc);
1106 vex_printf("] 0x%llx", i->Ain.Call.target);
1112 showAMD64CondCode(i->Ain.XDirect.cond));
1113 vex_printf("movabsq $0x%llx,%%r11; ", i->Ain.XDirect.dstGA);
1115 ppAMD64AMode(i->Ain.XDirect.amRIP);
1118 i->Ain.XDirect.toFastEP ? "fast" : "slow");
1123 showAMD64CondCode(i->Ain.XIndir.cond));
1125 ppHRegAMD64(i->Ain.XIndir.dstGA);
1127 ppAMD64AMode(i->Ain.XIndir.amRIP);
1133 showAMD64CondCode(i->Ain.XAssisted.cond));
1135 ppHRegAMD64(i->Ain.XAssisted.dstGA);
1137 ppAMD64AMode(i->Ain.XAssisted.amRIP);
1139 (Int)i->Ain.XAssisted.jk);
1144 vex_printf("cmov%s ", showAMD64CondCode(i->Ain.CMov64.cond));
1145 ppHRegAMD64(i->Ain.CMov64.src);
1147 ppHRegAMD64(i->Ain.CMov64.dst);
1151 showAMD64CondCode(i->Ain.CLoad.cond));
1152 vex_printf("mov%c ", i->Ain.CLoad.szB == 4 ? 'l' : 'q');
1153 ppAMD64AMode(i->Ain.CLoad.addr);
1155 (i->Ain.CLoad.szB == 4 ? ppHRegAMD64_lo32 : ppHRegAMD64)
1156 (i->Ain.CLoad.dst);
1161 showAMD64CondCode(i->Ain.CStore.cond));
1162 vex_printf("mov%c ", i->Ain.CStore.szB == 4 ? 'l' : 'q');
1163 (i->Ain.CStore.szB == 4 ? ppHRegAMD64_lo32 : ppHRegAMD64)
1164 (i->Ain.CStore.src);
1166 ppAMD64AMode(i->Ain.CStore.addr);
1171 vex_printf("mov%clq ", i->Ain.MovxLQ.syned ? 's' : 'z');
1172 ppHRegAMD64_lo32(i->Ain.MovxLQ.src);
1174 ppHRegAMD64(i->Ain.MovxLQ.dst);
1177 if (i->Ain.LoadEX.szSmall==4 && !i->Ain.LoadEX.syned) {
1179 ppAMD64AMode(i->Ain.LoadEX.src);
1181 ppHRegAMD64_lo32(i->Ain.LoadEX.dst);
1184 i->Ain.LoadEX.syned ? 's' : 'z',
1185 i->Ain.LoadEX.szSmall==1
1187 : (i->Ain.LoadEX.szSmall==2 ? 'w' : 'l'));
1188 ppAMD64AMode(i->Ain.LoadEX.src);
1190 ppHRegAMD64(i->Ain.LoadEX.dst);
1194 vex_printf("mov%c ", i->Ain.Store.sz==1 ? 'b'
1195 : (i->Ain.Store.sz==2 ? 'w' : 'l'));
1196 ppHRegAMD64(i->Ain.Store.src);
1198 ppAMD64AMode(i->Ain.Store.dst);
1201 vex_printf("setq%s ", showAMD64CondCode(i->Ain.Set64.cond));
1202 ppHRegAMD64(i->Ain.Set64.dst);
1205 vex_printf("bs%cq ", i->Ain.Bsfr64.isFwds ? 'f' : 'r');
1206 ppHRegAMD64(i->Ain.Bsfr64.src);
1208 ppHRegAMD64(i->Ain.Bsfr64.dst);
1215 i->Ain.ACAS.sz==1 ? 'b' : i->Ain.ACAS.sz==2 ? 'w'
1216 : i->Ain.ACAS.sz==4 ? 'l' : 'q' );
1218 ppAMD64AMode(i->Ain.ACAS.addr);
1222 (Int)(2 * i->Ain.DACAS.sz));
1223 ppAMD64AMode(i->Ain.DACAS.addr);
1226 vex_printf("ffree %%st(7..%d)", 8 - i->Ain.A87Free.nregs );
1229 vex_printf(i->Ain.A87PushPop.isPush ? "fld%c " : "fstp%c ",
1230 i->Ain.A87PushPop.szB == 4 ? 's' : 'l');
1231 ppAMD64AMode(i->Ain.A87PushPop.addr);
1234 vex_printf("f%s", showA87FpOp(i->Ain.A87FpOp.op));
1238 ppAMD64AMode(i->Ain.A87LdCW.addr);
1242 ppAMD64AMode(i->Ain.A87StSW.addr);
1246 ppAMD64AMode(i->Ain.LdMXCSR.addr);
1249 vex_printf("ucomis%s ", i->Ain.SseUComIS.sz==4 ? "s" : "d");
1250 ppHRegAMD64(i->Ain.SseUComIS.srcL);
1252 ppHRegAMD64(i->Ain.SseUComIS.srcR);
1254 ppHRegAMD64(i->Ain.SseUComIS.dst);
1257 vex_printf("cvtsi2s%s ", i->Ain.SseSI2SF.szD==4 ? "s" : "d");
1258 (i->Ain.SseSI2SF.szS==4 ? ppHRegAMD64_lo32 : ppHRegAMD64)
1259 (i->Ain.SseSI2SF.src);
1261 ppHRegAMD64(i->Ain.SseSI2SF.dst);
1264 vex_printf("cvts%s2si ", i->Ain.SseSF2SI.szS==4 ? "s" : "d");
1265 ppHRegAMD64(i->Ain.SseSF2SI.src);
1267 (i->Ain.SseSF2SI.szD==4 ? ppHRegAMD64_lo32 : ppHRegAMD64)
1268 (i->Ain.SseSF2SI.dst);
1271 vex_printf(i->Ain.SseSDSS.from64 ? "cvtsd2ss " : "cvtss2sd ");
1272 ppHRegAMD64(i->Ain.SseSDSS.src);
1274 ppHRegAMD64(i->Ain.SseSDSS.dst);
1277 switch (i->Ain.SseLdSt.sz) {
1283 if (i->Ain.SseLdSt.isLoad) {
1284 ppAMD64AMode(i->Ain.SseLdSt.addr);
1286 ppHRegAMD64(i->Ain.SseLdSt.reg);
1288 ppHRegAMD64(i->Ain.SseLdSt.reg);
1290 ppAMD64AMode(i->Ain.SseLdSt.addr);
1295 showAMD64CondCode(i->Ain.SseCStore.cond));
1297 ppHRegAMD64(i->Ain.SseCStore.src);
1299 ppAMD64AMode(i->Ain.SseCStore.addr);
1304 showAMD64CondCode(i->Ain.SseCLoad.cond));
1306 ppAMD64AMode(i->Ain.SseCLoad.addr);
1308 ppHRegAMD64(i->Ain.SseCLoad.dst);
1312 vex_printf("movs%s ", i->Ain.SseLdzLO.sz==4 ? "s" : "d");
1313 ppAMD64AMode(i->Ain.SseLdzLO.addr);
1315 ppHRegAMD64(i->Ain.SseLdzLO.reg);
1318 vex_printf("%sps ", showAMD64SseOp(i->Ain.Sse32Fx4.op));
1319 ppHRegAMD64(i->Ain.Sse32Fx4.src);
1321 ppHRegAMD64(i->Ain.Sse32Fx4.dst);
1324 vex_printf("%sss ", showAMD64SseOp(i->Ain.Sse32FLo.op));
1325 ppHRegAMD64(i->Ain.Sse32FLo.src);
1327 ppHRegAMD64(i->Ain.Sse32FLo.dst);
1330 vex_printf("%spd ", showAMD64SseOp(i->Ain.Sse64Fx2.op));
1331 ppHRegAMD64(i->Ain.Sse64Fx2.src);
1333 ppHRegAMD64(i->Ain.Sse64Fx2.dst);
1336 vex_printf("%ssd ", showAMD64SseOp(i->Ain.Sse64FLo.op));
1337 ppHRegAMD64(i->Ain.Sse64FLo.src);
1339 ppHRegAMD64(i->Ain.Sse64FLo.dst);
1342 vex_printf("%s ", showAMD64SseOp(i->Ain.SseReRg.op));
1343 ppHRegAMD64(i->Ain.SseReRg.src);
1345 ppHRegAMD64(i->Ain.SseReRg.dst);
1348 vex_printf("cmov%s ", showAMD64CondCode(i->Ain.SseCMov.cond));
1349 ppHRegAMD64(i->Ain.SseCMov.src);
1351 ppHRegAMD64(i->Ain.SseCMov.dst);
1354 vex_printf("pshufd $0x%x,", (UInt)i->Ain.SseShuf.order);
1355 ppHRegAMD64(i->Ain.SseShuf.src);
1357 ppHRegAMD64(i->Ain.SseShuf.dst);
1361 //uu if (i->Ain.AvxLdSt.isLoad) {
1362 //uu ppAMD64AMode(i->Ain.AvxLdSt.addr);
1364 //uu ppHRegAMD64(i->Ain.AvxLdSt.reg);
1366 //uu ppHRegAMD64(i->Ain.AvxLdSt.reg);
1368 //uu ppAMD64AMode(i->Ain.AvxLdSt.addr);
1372 //uu vex_printf("v%s ", showAMD64SseOp(i->Ain.SseReRg.op));
1373 //uu ppHRegAMD64(i->Ain.AvxReRg.src);
1375 //uu ppHRegAMD64(i->Ain.AvxReRg.dst);
1379 ppAMD64AMode(i->Ain.EvCheck.amCounter);
1381 ppAMD64AMode(i->Ain.EvCheck.amFailAddr);
1401 addHRegUse(u, HRmWrite, i->Ain.Imm64.dst);
1404 addRegUsage_AMD64RMI(u, i->Ain.Alu64R.src);
1405 if (i->Ain.Alu64R.op == Aalu_MOV) {
1406 addHRegUse(u, HRmWrite, i->Ain.Alu64R.dst);
1409 if (i->Ain.Alu64R.op == Aalu_CMP) {
1410 addHRegUse(u, HRmRead, i->Ain.Alu64R.dst);
1413 addHRegUse(u, HRmModify, i->Ain.Alu64R.dst);
1416 addRegUsage_AMD64RI(u, i->Ain.Alu64M.src);
1417 addRegUsage_AMD64AMode(u, i->Ain.Alu64M.dst);
1420 addHRegUse(u, HRmModify, i->Ain.Sh64.dst);
1421 if (i->Ain.Sh64.src == 0)
1425 addHRegUse(u, HRmRead, i->Ain.Test64.dst);
1428 addHRegUse(u, HRmModify, i->Ain.Unary64.dst);
1431 addRegUsage_AMD64AMode(u, i->Ain.Lea64.am);
1432 addHRegUse(u, HRmWrite, i->Ain.Lea64.dst);
1435 vassert(i->Ain.Alu32R.op != Aalu_MOV);
1436 addRegUsage_AMD64RMI(u, i->Ain.Alu32R.src);
1437 if (i->Ain.Alu32R.op == Aalu_CMP) {
1438 addHRegUse(u, HRmRead, i->Ain.Alu32R.dst);
1441 addHRegUse(u, HRmModify, i->Ain.Alu32R.dst);
1444 addRegUsage_AMD64RM(u, i->Ain.MulL.src, HRmRead);
1449 addRegUsage_AMD64RM(u, i->Ain.Div.src, HRmRead);
1454 addRegUsage_AMD64RMI(u, i->Ain.Push.src);
1488 switch (i->Ain.Call.regparms) {
1514 addRegUsage_AMD64AMode(u, i->Ain.XDirect.amRIP);
1518 addHRegUse(u, HRmRead, i->Ain.XIndir.dstGA);
1519 addRegUsage_AMD64AMode(u, i->Ain.XIndir.amRIP);
1523 addHRegUse(u, HRmRead, i->Ain.XAssisted.dstGA);
1524 addRegUsage_AMD64AMode(u, i->Ain.XAssisted.amRIP);
1527 addHRegUse(u, HRmRead, i->Ain.CMov64.src);
1528 addHRegUse(u, HRmModify, i->Ain.CMov64.dst);
1531 addRegUsage_AMD64AMode(u, i->Ain.CLoad.addr);
1532 addHRegUse(u, HRmModify, i->Ain.CLoad.dst);
1535 addRegUsage_AMD64AMode(u, i->Ain.CStore.addr);
1536 addHRegUse(u, HRmRead, i->Ain.CStore.src);
1539 addHRegUse(u, HRmRead, i->Ain.MovxLQ.src);
1540 addHRegUse(u, HRmWrite, i->Ain.MovxLQ.dst);
1543 addRegUsage_AMD64AMode(u, i->Ain.LoadEX.src);
1544 addHRegUse(u, HRmWrite, i->Ain.LoadEX.dst);
1547 addHRegUse(u, HRmRead, i->Ain.Store.src);
1548 addRegUsage_AMD64AMode(u, i->Ain.Store.dst);
1551 addHRegUse(u, HRmWrite, i->Ain.Set64.dst);
1554 addHRegUse(u, HRmRead, i->Ain.Bsfr64.src);
1555 addHRegUse(u, HRmWrite, i->Ain.Bsfr64.dst);
1560 addRegUsage_AMD64AMode(u, i->Ain.ACAS.addr);
1565 addRegUsage_AMD64AMode(u, i->Ain.DACAS.addr);
1574 addRegUsage_AMD64AMode(u, i->Ain.A87PushPop.addr);
1579 addRegUsage_AMD64AMode(u, i->Ain.A87LdCW.addr);
1582 addRegUsage_AMD64AMode(u, i->Ain.A87StSW.addr);
1585 addRegUsage_AMD64AMode(u, i->Ain.LdMXCSR.addr);
1588 addHRegUse(u, HRmRead, i->Ain.SseUComIS.srcL);
1589 addHRegUse(u, HRmRead, i->Ain.SseUComIS.srcR);
1590 addHRegUse(u, HRmWrite, i->Ain.SseUComIS.dst);
1593 addHRegUse(u, HRmRead, i->Ain.SseSI2SF.src);
1594 addHRegUse(u, HRmWrite, i->Ain.SseSI2SF.dst);
1597 addHRegUse(u, HRmRead, i->Ain.SseSF2SI.src);
1598 addHRegUse(u, HRmWrite, i->Ain.SseSF2SI.dst);
1601 addHRegUse(u, HRmRead, i->Ain.SseSDSS.src);
1602 addHRegUse(u, HRmWrite, i->Ain.SseSDSS.dst);
1605 addRegUsage_AMD64AMode(u, i->Ain.SseLdSt.addr);
1606 addHRegUse(u, i->Ain.SseLdSt.isLoad ? HRmWrite : HRmRead,
1607 i->Ain.SseLdSt.reg);
1610 addRegUsage_AMD64AMode(u, i->Ain.SseCStore.addr);
1611 addHRegUse(u, HRmRead, i->Ain.SseCStore.src);
1614 addRegUsage_AMD64AMode(u, i->Ain.SseCLoad.addr);
1615 addHRegUse(u, HRmModify, i->Ain.SseCLoad.dst);
1618 addRegUsage_AMD64AMode(u, i->Ain.SseLdzLO.addr);
1619 addHRegUse(u, HRmWrite, i->Ain.SseLdzLO.reg);
1622 vassert(i->Ain.Sse32Fx4.op != Asse_MOV);
1623 unary = toBool( i->Ain.Sse32Fx4.op == Asse_RCPF
1624 || i->Ain.Sse32Fx4.op == Asse_RSQRTF
1625 || i->Ain.Sse32Fx4.op == Asse_SQRTF );
1626 addHRegUse(u, HRmRead, i->Ain.Sse32Fx4.src);
1628 i->Ain.Sse32Fx4.dst);
1631 vassert(i->Ain.Sse32FLo.op != Asse_MOV);
1632 unary = toBool( i->Ain.Sse32FLo.op == Asse_RCPF
1633 || i->Ain.Sse32FLo.op == Asse_RSQRTF
1634 || i->Ain.Sse32FLo.op == Asse_SQRTF );
1635 addHRegUse(u, HRmRead, i->Ain.Sse32FLo.src);
1637 i->Ain.Sse32FLo.dst);
1640 vassert(i->Ain.Sse64Fx2.op != Asse_MOV);
1641 unary = toBool( i->Ain.Sse64Fx2.op == Asse_RCPF
1642 || i->Ain.Sse64Fx2.op == Asse_RSQRTF
1643 || i->Ain.Sse64Fx2.op == Asse_SQRTF );
1644 addHRegUse(u, HRmRead, i->Ain.Sse64Fx2.src);
1646 i->Ain.Sse64Fx2.dst);
1649 vassert(i->Ain.Sse64FLo.op != Asse_MOV);
1650 unary = toBool( i->Ain.Sse64FLo.op == Asse_RCPF
1651 || i->Ain.Sse64FLo.op == Asse_RSQRTF
1652 || i->Ain.Sse64FLo.op == Asse_SQRTF );
1653 addHRegUse(u, HRmRead, i->Ain.Sse64FLo.src);
1655 i->Ain.Sse64FLo.dst);
1658 if ( (i->Ain.SseReRg.op == Asse_XOR
1659 || i->Ain.SseReRg.op == Asse_CMPEQ32)
1660 && sameHReg(i->Ain.SseReRg.src, i->Ain.SseReRg.dst)) {
1665 addHRegUse(u, HRmWrite, i->Ain.SseReRg.dst);
1667 addHRegUse(u, HRmRead, i->Ain.SseReRg.src);
1668 addHRegUse(u, i->Ain.SseReRg.op == Asse_MOV
1670 i->Ain.SseReRg.dst);
1674 addHRegUse(u, HRmRead, i->Ain.SseCMov.src);
1675 addHRegUse(u, HRmModify, i->Ain.SseCMov.dst);
1678 addHRegUse(u, HRmRead, i->Ain.SseShuf.src);
1679 addHRegUse(u, HRmWrite, i->Ain.SseShuf.dst);
1682 //uu addRegUsage_AMD64AMode(u, i->Ain.AvxLdSt.addr);
1683 //uu addHRegUse(u, i->Ain.AvxLdSt.isLoad ? HRmWrite : HRmRead,
1684 //uu i->Ain.AvxLdSt.reg);
1687 //uu if ( (i->Ain.AvxReRg.op == Asse_XOR
1688 //uu || i->Ain.AvxReRg.op == Asse_CMPEQ32)
1689 //uu && i->Ain.AvxReRg.src == i->Ain.AvxReRg.dst) {
1691 //uu addHRegUse(u, HRmWrite, i->Ain.AvxReRg.dst);
1693 //uu addHRegUse(u, HRmRead, i->Ain.AvxReRg.src);
1694 //uu addHRegUse(u, i->Ain.AvxReRg.op == Asse_MOV
1696 //uu i->Ain.AvxReRg.dst);
1702 addRegUsage_AMD64AMode(u, i->Ain.EvCheck.amCounter);
1703 addRegUsage_AMD64AMode(u, i->Ain.EvCheck.amFailAddr);
1725 mapReg(m, &i->Ain.Imm64.dst);
1728 mapRegs_AMD64RMI(m, i->Ain.Alu64R.src);
1729 mapReg(m, &i->Ain.Alu64R.dst);
1732 mapRegs_AMD64RI(m, i->Ain.Alu64M.src);
1733 mapRegs_AMD64AMode(m, i->Ain.Alu64M.dst);
1736 mapReg(m, &i->Ain.Sh64.dst);
1739 mapReg(m, &i->Ain.Test64.dst);
1742 mapReg(m, &i->Ain.Unary64.dst);
1745 mapRegs_AMD64AMode(m, i->Ain.Lea64.am);
1746 mapReg(m, &i->Ain.Lea64.dst);
1749 mapRegs_AMD64RMI(m, i->Ain.Alu32R.src);
1750 mapReg(m, &i->Ain.Alu32R.dst);
1753 mapRegs_AMD64RM(m, i->Ain.MulL.src);
1756 mapRegs_AMD64RM(m, i->Ain.Div.src);
1759 mapRegs_AMD64RMI(m, i->Ain.Push.src);
1764 mapRegs_AMD64AMode(m, i->Ain.XDirect.amRIP);
1767 mapReg(m, &i->Ain.XIndir.dstGA);
1768 mapRegs_AMD64AMode(m, i->Ain.XIndir.amRIP);
1771 mapReg(m, &i->Ain.XAssisted.dstGA);
1772 mapRegs_AMD64AMode(m, i->Ain.XAssisted.amRIP);
1775 mapReg(m, &i->Ain.CMov64.src);
1776 mapReg(m, &i->Ain.CMov64.dst);
1779 mapRegs_AMD64AMode(m, i->Ain.CLoad.addr);
1780 mapReg(m, &i->Ain.CLoad.dst);
1783 mapRegs_AMD64AMode(m, i->Ain.CStore.addr);
1784 mapReg(m, &i->Ain.CStore.src);
1787 mapReg(m, &i->Ain.MovxLQ.src);
1788 mapReg(m, &i->Ain.MovxLQ.dst);
1791 mapRegs_AMD64AMode(m, i->Ain.LoadEX.src);
1792 mapReg(m, &i->Ain.LoadEX.dst);
1795 mapReg(m, &i->Ain.Store.src);
1796 mapRegs_AMD64AMode(m, i->Ain.Store.dst);
1799 mapReg(m, &i->Ain.Set64.dst);
1802 mapReg(m, &i->Ain.Bsfr64.src);
1803 mapReg(m, &i->Ain.Bsfr64.dst);
1808 mapRegs_AMD64AMode(m, i->Ain.ACAS.addr);
1811 mapRegs_AMD64AMode(m, i->Ain.DACAS.addr);
1816 mapRegs_AMD64AMode(m, i->Ain.A87PushPop.addr);
1821 mapRegs_AMD64AMode(m, i->Ain.A87LdCW.addr);
1824 mapRegs_AMD64AMode(m, i->Ain.A87StSW.addr);
1827 mapRegs_AMD64AMode(m, i->Ain.LdMXCSR.addr);
1830 mapReg(m, &i->Ain.SseUComIS.srcL);
1831 mapReg(m, &i->Ain.SseUComIS.srcR);
1832 mapReg(m, &i->Ain.SseUComIS.dst);
1835 mapReg(m, &i->Ain.SseSI2SF.src);
1836 mapReg(m, &i->Ain.SseSI2SF.dst);
1839 mapReg(m, &i->Ain.SseSF2SI.src);
1840 mapReg(m, &i->Ain.SseSF2SI.dst);
1843 mapReg(m, &i->Ain.SseSDSS.src);
1844 mapReg(m, &i->Ain.SseSDSS.dst);
1847 mapReg(m, &i->Ain.SseLdSt.reg);
1848 mapRegs_AMD64AMode(m, i->Ain.SseLdSt.addr);
1851 mapRegs_AMD64AMode(m, i->Ain.SseCStore.addr);
1852 mapReg(m, &i->Ain.SseCStore.src);
1855 mapRegs_AMD64AMode(m, i->Ain.SseCLoad.addr);
1856 mapReg(m, &i->Ain.SseCLoad.dst);
1859 mapReg(m, &i->Ain.SseLdzLO.reg);
1860 mapRegs_AMD64AMode(m, i->Ain.SseLdzLO.addr);
1863 mapReg(m, &i->Ain.Sse32Fx4.src);
1864 mapReg(m, &i->Ain.Sse32Fx4.dst);
1867 mapReg(m, &i->Ain.Sse32FLo.src);
1868 mapReg(m, &i->Ain.Sse32FLo.dst);
1871 mapReg(m, &i->Ain.Sse64Fx2.src);
1872 mapReg(m, &i->Ain.Sse64Fx2.dst);
1875 mapReg(m, &i->Ain.Sse64FLo.src);
1876 mapReg(m, &i->Ain.Sse64FLo.dst);
1879 mapReg(m, &i->Ain.SseReRg.src);
1880 mapReg(m, &i->Ain.SseReRg.dst);
1883 mapReg(m, &i->Ain.SseCMov.src);
1884 mapReg(m, &i->Ain.SseCMov.dst);
1887 mapReg(m, &i->Ain.SseShuf.src);
1888 mapReg(m, &i->Ain.SseShuf.dst);
1891 //uu mapReg(m, &i->Ain.AvxLdSt.reg);
1892 //uu mapRegs_AMD64AMode(m, i->Ain.AvxLdSt.addr);
1895 //uu mapReg(m, &i->Ain.AvxReRg.src);
1896 //uu mapReg(m, &i->Ain.AvxReRg.dst);
1901 mapRegs_AMD64AMode(m, i->Ain.EvCheck.amCounter);
1902 mapRegs_AMD64AMode(m, i->Ain.EvCheck.amFailAddr);
1922 if (i->Ain.Alu64R.op != Aalu_MOV)
1924 if (i->Ain.Alu64R.src->tag != Armi_Reg)
1926 *src = i->Ain.Alu64R.src->Armi.Reg.reg;
1927 *dst = i->Ain.Alu64R.dst;
1931 if (i->Ain.SseReRg.op != Asse_MOV)
1933 *src = i->Ain.SseReRg.src;
1934 *dst = i->Ain.SseReRg.dst;
1938 //uu if (i->Ain.AvxReRg.op != Asse_MOV)
1940 //uu *src = i->Ain.AvxReRg.src;
1941 //uu *dst = i->Ain.AvxReRg.dst;
2433 if (i->Ain.Imm64.imm64 <= 0xFFFFFULL) {
2438 if (1 & iregEnc3(i->Ain.Imm64.dst))
2440 *p++ = 0xB8 + iregEnc210(i->Ain.Imm64.dst);
2441 p = emit32(p, (UInt)i->Ain.Imm64.imm64);
2443 *p++ = toUChar(0x48 + (1 & iregEnc3(i->Ain.Imm64.dst)));
2444 *p++ = toUChar(0xB8 + iregEnc210(i->Ain.Imm64.dst));
2445 p = emit64(p, i->Ain.Imm64.imm64);
2451 if (i->Ain.Alu64R.op == Aalu_MOV) {
2452 switch (i->Ain.Alu64R.src->tag) {
2454 if (0 == (i->Ain.Alu64R.src->Armi.Imm.imm32 & ~0xFFFFF)) {
2464 if (1 & iregEnc3(i->Ain.Alu64R.dst))
2466 *p++ = 0xB8 + iregEnc210(i->Ain.Alu64R.dst);
2467 p = emit32(p, i->Ain.Alu64R.src->Armi.Imm.imm32);
2469 *p++ = toUChar(0x48 + (1 & iregEnc3(i->Ain.Alu64R.dst)));
2471 *p++ = toUChar(0xC0 + iregEnc210(i->Ain.Alu64R.dst));
2472 p = emit32(p, i->Ain.Alu64R.src->Armi.Imm.imm32);
2476 *p++ = rexAMode_R( i->Ain.Alu64R.src->Armi.Reg.reg,
2477 i->Ain.Alu64R.dst );
2479 p = doAMode_R(p, i->Ain.Alu64R.src->Armi.Reg.reg,
2480 i->Ain.Alu64R.dst);
2483 *p++ = rexAMode_M(i->Ain.Alu64R.dst,
2484 i->Ain.Alu64R.src->Armi.Mem.am);
2486 p = doAMode_M(p, i->Ain.Alu64R.dst,
2487 i->Ain.Alu64R.src->Armi.Mem.am);
2494 if (i->Ain.Alu64R.op == Aalu_MUL) {
2495 switch (i->Ain.Alu64R.src->tag) {
2497 *p++ = rexAMode_R( i->Ain.Alu64R.dst,
2498 i->Ain.Alu64R.src->Armi.Reg.reg);
2501 p = doAMode_R(p, i->Ain.Alu64R.dst,
2502 i->Ain.Alu64R.src->Armi.Reg.reg);
2505 *p++ = rexAMode_M(i->Ain.Alu64R.dst,
2506 i->Ain.Alu64R.src->Armi.Mem.am);
2509 p = doAMode_M(p, i->Ain.Alu64R.dst,
2510 i->Ain.Alu64R.src->Armi.Mem.am);
2513 if (fits8bits(i->Ain.Alu64R.src->Armi.Imm.imm32)) {
2514 *p++ = rexAMode_R(i->Ain.Alu64R.dst, i->Ain.Alu64R.dst);
2516 p = doAMode_R(p, i->Ain.Alu64R.dst, i->Ain.Alu64R.dst);
2517 *p++ = toUChar(0xFF & i->Ain.Alu64R.src->Armi.Imm.imm32);
2519 *p++ = rexAMode_R(i->Ain.Alu64R.dst, i->Ain.Alu64R.dst);
2521 p = doAMode_R(p, i->Ain.Alu64R.dst, i->Ain.Alu64R.dst);
2522 p = emit32(p, i->Ain.Alu64R.src->Armi.Imm.imm32);
2531 switch (i->Ain.Alu64R.op) {
2550 switch (i->Ain.Alu64R.src->tag) {
2552 if (sameHReg(i->Ain.Alu64R.dst, hregAMD64_RAX())
2553 && !fits8bits(i->Ain.Alu64R.src->Armi.Imm.imm32)) {
2556 p = emit32(p, i->Ain.Alu64R.src->Armi.Imm.imm32);
2558 if (fits8bits(i->Ain.Alu64R.src->Armi.Imm.imm32)) {
2559 *p++ = rexAMode_R_enc_reg( 0, i->Ain.Alu64R.dst );
2561 p = doAMode_R_enc_reg(p, subopc_imm, i->Ain.Alu64R.dst);
2562 *p++ = toUChar(0xFF & i->Ain.Alu64R.src->Armi.Imm.imm32);
2564 *p++ = rexAMode_R_enc_reg( 0, i->Ain.Alu64R.dst);
2566 p = doAMode_R_enc_reg(p, subopc_imm, i->Ain.Alu64R.dst);
2567 p = emit32(p, i->Ain.Alu64R.src->Armi.Imm.imm32);
2571 *p++ = rexAMode_R( i->Ain.Alu64R.src->Armi.Reg.reg,
2572 i->Ain.Alu64R.dst);
2574 p = doAMode_R(p, i->Ain.Alu64R.src->Armi.Reg.reg,
2575 i->Ain.Alu64R.dst);
2578 *p++ = rexAMode_M( i->Ain.Alu64R.dst,
2579 i->Ain.Alu64R.src->Armi.Mem.am);
2581 p = doAMode_M(p, i->Ain.Alu64R.dst,
2582 i->Ain.Alu64R.src->Armi.Mem.am);
2591 if (i->Ain.Alu64M.op == Aalu_MOV) {
2592 switch (i->Ain.Alu64M.src->tag) {
2594 *p++ = rexAMode_M(i->Ain.Alu64M.src->Ari.Reg.reg,
2595 i->Ain.Alu64M.dst);
2597 p = doAMode_M(p, i->Ain.Alu64M.src->Ari.Reg.reg,
2598 i->Ain.Alu64M.dst);
2601 *p++ = rexAMode_M_enc(0, i->Ain.Alu64M.dst);
2603 p = doAMode_M_enc(p, 0, i->Ain.Alu64M.dst);
2604 p = emit32(p, i->Ain.Alu64M.src->Ari.Imm.imm32);
2614 switch (i->Ain.Sh64.op) {
2620 if (i->Ain.Sh64.src == 0) {
2621 *p++ = rexAMode_R_enc_reg(0, i->Ain.Sh64.dst);
2623 p = doAMode_R_enc_reg(p, subopc, i->Ain.Sh64.dst);
2626 *p++ = rexAMode_R_enc_reg(0, i->Ain.Sh64.dst);
2628 p = doAMode_R_enc_reg(p, subopc, i->Ain.Sh64.dst);
2629 *p++ = (UChar)(i->Ain.Sh64.src);
2636 *p++ = rexAMode_R_enc_reg(0, i->Ain.Test64.dst);
2638 p = doAMode_R_enc_reg(p, 0, i->Ain.Test64.dst);
2639 p = emit32(p, i->Ain.Test64.imm32);
2643 if (i->Ain.Unary64.op == Aun_NOT) {
2644 *p++ = rexAMode_R_enc_reg(0, i->Ain.Unary64.dst);
2646 p = doAMode_R_enc_reg(p, 2, i->Ain.Unary64.dst);
2649 if (i->Ain.Unary64.op == Aun_NEG) {
2650 *p++ = rexAMode_R_enc_reg(0, i->Ain.Unary64.dst);
2652 p = doAMode_R_enc_reg(p, 3, i->Ain.Unary64.dst);
2658 *p++ = rexAMode_M(i->Ain.Lea64.dst, i->Ain.Lea64.am);
2660 p = doAMode_M(p, i->Ain.Lea64.dst, i->Ain.Lea64.am);
2666 switch (i->Ain.Alu32R.op) {
2681 switch (i->Ain.Alu32R.src->tag) {
2683 if (sameHReg(i->Ain.Alu32R.dst, hregAMD64_RAX())
2684 && !fits8bits(i->Ain.Alu32R.src->Armi.Imm.imm32)) {
2687 p = emit32(p, i->Ain.Alu32R.src->Armi.Imm.imm32);
2689 if (fits8bits(i->Ain.Alu32R.src->Armi.Imm.imm32)) {
2690 rex = clearWBit( rexAMode_R_enc_reg( 0, i->Ain.Alu32R.dst ) );
2693 p = doAMode_R_enc_reg(p, subopc_imm, i->Ain.Alu32R.dst);
2694 *p++ = toUChar(0xFF & i->Ain.Alu32R.src->Armi.Imm.imm32);
2696 rex = clearWBit( rexAMode_R_enc_reg( 0, i->Ain.Alu32R.dst) );
2699 p = doAMode_R_enc_reg(p, subopc_imm, i->Ain.Alu32R.dst);
2700 p = emit32(p, i->Ain.Alu32R.src->Armi.Imm.imm32);
2705 rexAMode_R( i->Ain.Alu32R.src->Armi.Reg.reg,
2706 i->Ain.Alu32R.dst) );
2709 p = doAMode_R(p, i->Ain.Alu32R.src->Armi.Reg.reg,
2710 i->Ain.Alu32R.dst);
2714 rexAMode_M( i->Ain.Alu32R.dst,
2715 i->Ain.Alu32R.src->Armi.Mem.am) );
2718 p = doAMode_M(p, i->Ain.Alu32R.dst,
2719 i->Ain.Alu32R.src->Armi.Mem.am);
2727 subopc = i->Ain.MulL.syned ? 5 : 4;
2728 switch (i->Ain.MulL.src->tag) {
2730 *p++ = rexAMode_M_enc(0, i->Ain.MulL.src->Arm.Mem.am);
2732 p = doAMode_M_enc(p, subopc, i->Ain.MulL.src->Arm.Mem.am);
2735 *p++ = rexAMode_R_enc_reg(0, i->Ain.MulL.src->Arm.Reg.reg);
2737 p = doAMode_R_enc_reg(p, subopc, i->Ain.MulL.src->Arm.Reg.reg);
2745 subopc = i->Ain.Div.syned ? 7 : 6;
2746 if (i->Ain.Div.sz == 4) {
2747 switch (i->Ain.Div.src->tag) {
2752 p = doAMode_M_enc(p, subopc, i->Ain.Div.src->Arm.Mem.am);
2756 rexAMode_R_enc_reg(0, i->Ain.Div.src->Arm.Reg.reg));
2758 p = doAMode_R_enc_reg(p, subopc, i->Ain.Div.src->Arm.Reg.reg);
2764 if (i->Ain.Div.sz == 8) {
2765 switch (i->Ain.Div.src->tag) {
2767 *p++ = rexAMode_M_enc(0, i->Ain.Div.src->Arm.Mem.am);
2769 p = doAMode_M_enc(p, subopc, i->Ain.Div.src->Arm.Mem.am);
2772 *p++ = rexAMode_R_enc_reg(0, i->Ain.Div.src->Arm.Reg.reg);
2774 p = doAMode_R_enc_reg(p, subopc, i->Ain.Div.src->Arm.Reg.reg);
2783 switch (i->Ain.Push.src->tag) {
2786 rexAMode_M_enc(0, i->Ain.Push.src->Armi.Mem.am));
2788 p = doAMode_M_enc(p, 6, i->Ain.Push.src->Armi.Mem.am);
2792 p = emit32(p, i->Ain.Push.src->Armi.Imm.imm32);
2795 *p++ = toUChar(0x40 + (1 & iregEnc3(i->Ain.Push.src->Armi.Reg.reg)));
2796 *p++ = toUChar(0x50 + iregEnc210(i->Ain.Push.src->Armi.Reg.reg));
2808 if (i->Ain.Call.cond == Acc_ALWAYS/*call always happens*/
2809 || i->Ain.Call.rloc.pri == RLPri_None/*no fixup action*/) {
2812 Bool shortImm = fitsIn32Bits(i->Ain.Call.target);
2813 if (i->Ain.Call.cond != Acc_ALWAYS) {
2814 *p++ = toUChar(0x70 + (0xF & (i->Ain.Call.cond ^ 1)));
2823 p = emit32(p, (UInt)i->Ain.Call.target);
2828 p = emit64(p, i->Ain.Call.target);
2852 *p++ = toUChar(0x70 + (0xF & (i->Ain.Call.cond ^ 1)));
2858 p = emit64(p, i->Ain.Call.target);
2876 switch (i->Ain.Call.rloc.pri) {
2889 if (i->Ain.Call.rloc.spOff == 0) {
2949 if (i->Ain.XDirect.cond != Acc_ALWAYS) {
2951 *p++ = toUChar(0x70 + (0xF & (i->Ain.XDirect.cond ^ 1)));
2957 if (fitsIn32Bits(i->Ain.XDirect.dstGA)) {
2963 p = emit32(p, (UInt)i->Ain.XDirect.dstGA);
2968 p = emit64(p, i->Ain.XDirect.dstGA);
2972 *p++ = rexAMode_M(r11, i->Ain.XDirect.amRIP);
2974 p = doAMode_M(p, r11, i->Ain.XDirect.amRIP);
2985 = i->Ain.XDirect.toFastEP ? disp_cp_chain_me_to_fastEP
2995 if (i->Ain.XDirect.cond != Acc_ALWAYS) {
3017 if (i->Ain.XIndir.cond != Acc_ALWAYS) {
3019 *p++ = toUChar(0x70 + (0xF & (i->Ain.XIndir.cond ^ 1)));
3025 *p++ = rexAMode_M(i->Ain.XIndir.dstGA, i->Ain.XIndir.amRIP);
3027 p = doAMode_M(p, i->Ain.XIndir.dstGA, i->Ain.XIndir.amRIP);
3050 if (i->Ain.XIndir.cond != Acc_ALWAYS) {
3064 if (i->Ain.XAssisted.cond != Acc_ALWAYS) {
3066 *p++ = toUChar(0x70 + (0xF & (i->Ain.XAssisted.cond ^ 1)));
3072 *p++ = rexAMode_M(i->Ain.XAssisted.dstGA, i->Ain.XAssisted.amRIP);
3074 p = doAMode_M(p, i->Ain.XAssisted.dstGA, i->Ain.XAssisted.amRIP);
3079 switch (i->Ain.XAssisted.jk) {
3098 ppIRJumpKind(i->Ain.XAssisted.jk);
3114 if (i->Ain.XAssisted.cond != Acc_ALWAYS) {
3123 vassert(i->Ain.CMov64.cond != Acc_ALWAYS);
3124 *p++ = rexAMode_R(i->Ain.CMov64.dst, i->Ain.CMov64.src);
3126 *p++ = toUChar(0x40 + (0xF & i->Ain.CMov64.cond));
3127 p = doAMode_R(p, i->Ain.CMov64.dst, i->Ain.CMov64.src);
3131 vassert(i->Ain.CLoad.cond != Acc_ALWAYS);
3134 vassert(i->Ain.CLoad.szB == 4 || i->Ain.CLoad.szB == 8);
3140 *p++ = toUChar(0x70 + (0xF & (i->Ain.CLoad.cond ^ 1)));
3147 rex = rexAMode_M(i->Ain.CLoad.dst, i->Ain.CLoad.addr);
3148 *p++ = i->Ain.CLoad.szB == 4 ? clearWBit(rex) : rex;
3150 p = doAMode_M(p, i->Ain.CLoad.dst, i->Ain.CLoad.addr);
3162 vassert(i->Ain.CStore.cond != Acc_ALWAYS);
3165 vassert(i->Ain.CStore.szB == 4 || i->Ain.CStore.szB == 8);
3171 *p++ = toUChar(0x70 + (0xF & (i->Ain.CStore.cond ^ 1)));
3176 rex = rexAMode_M(i->Ain.CStore.src, i->Ain.CStore.addr);
3177 *p++ = i->Ain.CStore.szB == 4 ? clearWBit(rex) : rex;
3179 p = doAMode_M(p, i->Ain.CStore.src, i->Ain.CStore.addr);
3191 if (i->Ain.MovxLQ.syned) {
3193 *p++ = rexAMode_R(i->Ain.MovxLQ.dst, i->Ain.MovxLQ.src);
3195 p = doAMode_R(p, i->Ain.MovxLQ.dst, i->Ain.MovxLQ.src);
3200 rexAMode_R(i->Ain.MovxLQ.src, i->Ain.MovxLQ.dst));
3202 p = doAMode_R(p, i->Ain.MovxLQ.src, i->Ain.MovxLQ.dst);
3207 if (i->Ain.LoadEX.szSmall == 1 && !i->Ain.LoadEX.syned) {
3209 *p++ = rexAMode_M(i->Ain.LoadEX.dst, i->Ain.LoadEX.src);
3212 p = doAMode_M(p, i->Ain.LoadEX.dst, i->Ain.LoadEX.src);
3215 if (i->Ain.LoadEX.szSmall == 2 && !i->Ain.LoadEX.syned) {
3217 *p++ = rexAMode_M(i->Ain.LoadEX.dst, i->Ain.LoadEX.src);
3220 p = doAMode_M(p, i->Ain.LoadEX.dst, i->Ain.LoadEX.src);
3223 if (i->Ain.LoadEX.szSmall == 4 && !i->Ain.LoadEX.syned) {
3230 rexAMode_M(i->Ain.LoadEX.dst, i->Ain.LoadEX.src));
3232 p = doAMode_M(p, i->Ain.LoadEX.dst, i->Ain.LoadEX.src);
3243 reg = iregEnc3210(i->Ain.Set64.dst);
3256 *p++ = toUChar(0x90 + (0x0F & i->Ain.Set64.cond));
3261 *p++ = rexAMode_R(i->Ain.Bsfr64.dst, i->Ain.Bsfr64.src);
3263 if (i->Ain.Bsfr64.isFwds) {
3268 p = doAMode_R(p, i->Ain.Bsfr64.dst, i->Ain.Bsfr64.src);
3279 if (i->Ain.ACAS.sz == 2) *p++ = 0x66;
3285 rex = rexAMode_M( hregAMD64_RBX(), i->Ain.ACAS.addr );
3286 if (i->Ain.ACAS.sz != 8)
3291 if (i->Ain.ACAS.sz == 1) *p++ = 0xB0; else *p++ = 0xB1;
3292 p = doAMode_M(p, hregAMD64_RBX(), i->Ain.ACAS.addr);
3301 rex = rexAMode_M_enc(1, i->Ain.ACAS.addr );
3302 if (i->Ain.ACAS.sz != 8)
3307 p = doAMode_M_enc(p, 1, i->Ain.DACAS.addr);
3311 vassert(i->Ain.A87Free.nregs > 0 && i->Ain.A87Free.nregs <= 7);
3312 for (j = 0; j < i->Ain.A87Free.nregs; j++) {
3318 vassert(i->Ain.A87PushPop.szB == 8 || i->Ain.A87PushPop.szB == 4);
3319 if (i->Ain.A87PushPop.isPush) {
3322 rexAMode_M_enc(0, i->Ain.A87PushPop.addr) );
3323 *p++ = i->Ain.A87PushPop.szB == 4 ? 0xD9 : 0xDD;
3324 p = doAMode_M_enc(p, 0/*subopcode*/, i->Ain.A87PushPop.addr);
3328 rexAMode_M_enc(3, i->Ain.A87PushPop.addr) );
3329 *p++ = i->Ain.A87PushPop.szB == 4 ? 0xD9 : 0xDD;
3330 p = doAMode_M_enc(p, 3/*subopcode*/, i->Ain.A87PushPop.addr);
3336 switch (i->Ain.A87FpOp.op) {
3371 rexAMode_M_enc(5, i->Ain.A87LdCW.addr) );
3373 p = doAMode_M_enc(p, 5/*subopcode*/, i->Ain.A87LdCW.addr);
3378 rexAMode_M_enc(7, i->Ain.A87StSW.addr) );
3380 p = doAMode_M_enc(p, 7/*subopcode*/, i->Ain.A87StSW.addr);
3384 if (i->Ain.Store.sz == 2) {
3390 *p++ = clearWBit( rexAMode_M( i->Ain.Store.src, i->Ain.Store.dst) );
3392 p = doAMode_M(p, i->Ain.Store.src, i->Ain.Store.dst);
3395 if (i->Ain.Store.sz == 4) {
3396 *p++ = clearWBit( rexAMode_M( i->Ain.Store.src, i->Ain.Store.dst) );
3398 p = doAMode_M(p, i->Ain.Store.src, i->Ain.Store.dst);
3401 if (i->Ain.Store.sz == 1) {
3405 *p++ = clearWBit( rexAMode_M( i->Ain.Store.src, i->Ain.Store.dst) );
3407 p = doAMode_M(p, i->Ain.Store.src, i->Ain.Store.dst);
3413 *p++ = clearWBit(rexAMode_M_enc(0, i->Ain.LdMXCSR.addr));
3416 p = doAMode_M_enc(p, 2/*subopcode*/, i->Ain.LdMXCSR.addr);
3422 if (i->Ain.SseUComIS.sz == 8) {
3426 vassert(i->Ain.SseUComIS.sz == 4);
3429 rexAMode_R_enc_enc( vregEnc3210(i->Ain.SseUComIS.srcL),
3430 vregEnc3210(i->Ain.SseUComIS.srcR) ));
3433 p = doAMode_R_enc_enc(p, vregEnc3210(i->Ain.SseUComIS.srcL),
3434 vregEnc3210(i->Ain.SseUComIS.srcR) );
3438 *p++ = toUChar(0x40 + (1 & iregEnc3(i->Ain.SseUComIS.dst)));
3439 *p++ = toUChar(0x58 + iregEnc210(i->Ain.SseUComIS.dst));
3444 rex = rexAMode_R_enc_reg( vregEnc3210(i->Ain.SseSI2SF.dst),
3445 i->Ain.SseSI2SF.src );
3446 *p++ = toUChar(i->Ain.SseSI2SF.szD==4 ? 0xF3 : 0xF2);
3447 *p++ = toUChar(i->Ain.SseSI2SF.szS==4 ? clearWBit(rex) : rex);
3450 p = doAMode_R_enc_reg( p, vregEnc3210(i->Ain.SseSI2SF.dst),
3451 i->Ain.SseSI2SF.src );
3456 rex = rexAMode_R_reg_enc( i->Ain.SseSF2SI.dst,
3457 vregEnc3210(i->Ain.SseSF2SI.src) );
3458 *p++ = toUChar(i->Ain.SseSF2SI.szS==4 ? 0xF3 : 0xF2);
3459 *p++ = toUChar(i->Ain.SseSF2SI.szD==4 ? clearWBit(rex) : rex);
3462 p = doAMode_R_reg_enc( p, i->Ain.SseSF2SI.dst,
3463 vregEnc3210(i->Ain.SseSF2SI.src) );
3468 *p++ = toUChar(i->Ain.SseSDSS.from64 ? 0xF2 : 0xF3);
3470 rexAMode_R_enc_enc( vregEnc3210(i->Ain.SseSDSS.dst),
3471 vregEnc3210(i->Ain.SseSDSS.src) ));
3474 p = doAMode_R_enc_enc( p, vregEnc3210(i->Ain.SseSDSS.dst),
3475 vregEnc3210(i->Ain.SseSDSS.src) );
3479 if (i->Ain.SseLdSt.sz == 8) {
3482 if (i->Ain.SseLdSt.sz == 4) {
3485 if (i->Ain.SseLdSt.sz != 16) {
3489 rexAMode_M_enc(vregEnc3210(i->Ain.SseLdSt.reg),
3490 i->Ain.SseLdSt.addr));
3492 *p++ = toUChar(i->Ain.SseLdSt.isLoad ? 0x10 : 0x11);
3493 p = doAMode_M_enc(p, vregEnc3210(i->Ain.SseLdSt.reg),
3494 i->Ain.SseLdSt.addr);
3498 vassert(i->Ain.SseCStore.cond != Acc_ALWAYS);
3504 *p++ = toUChar(0x70 + (0xF & (i->Ain.SseCStore.cond ^ 1)));
3510 rexAMode_M_enc(vregEnc3210(i->Ain.SseCStore.src),
3511 i->Ain.SseCStore.addr));
3514 p = doAMode_M_enc(p, vregEnc3210(i->Ain.SseCStore.src),
3515 i->Ain.SseCStore.addr);
3525 vassert(i->Ain.SseCLoad.cond != Acc_ALWAYS);
3531 *p++ = toUChar(0x70 + (0xF & (i->Ain.SseCLoad.cond ^ 1)));
3537 rexAMode_M_enc(vregEnc3210(i->Ain.SseCLoad.dst),
3538 i->Ain.SseCLoad.addr));
3541 p = doAMode_M_enc(p, vregEnc3210(i->Ain.SseCLoad.dst),
3542 i->Ain.SseCLoad.addr);
3552 vassert(i->Ain.SseLdzLO.sz == 4 || i->Ain.SseLdzLO.sz == 8);
3554 *p++ = toUChar(i->Ain.SseLdzLO.sz==4 ? 0xF3 : 0xF2);
3556 rexAMode_M_enc(vregEnc3210(i->Ain.SseLdzLO.reg),
3557 i->Ain.SseLdzLO.addr));
3560 p = doAMode_M_enc(p, vregEnc3210(i->Ain.SseLdzLO.reg),
3561 i->Ain.SseLdzLO.addr);
3567 rexAMode_R_enc_enc( vregEnc3210(i->Ain.Sse32Fx4.dst),
3568 vregEnc3210(i->Ain.Sse32Fx4.src) ));
3570 switch (i->Ain.Sse32Fx4.op) {
3586 p = doAMode_R_enc_enc(p, vregEnc3210(i->Ain.Sse32Fx4.dst),
3587 vregEnc3210(i->Ain.Sse32Fx4.src) );
3596 rexAMode_R_enc_enc( vregEnc3210(i->Ain.Sse64Fx2.dst),
3597 vregEnc3210(i->Ain.Sse64Fx2.src) ));
3599 switch (i->Ain.Sse64Fx2.op) {
3613 p = doAMode_R_enc_enc(p, vregEnc3210(i->Ain.Sse64Fx2.dst),
3614 vregEnc3210(i->Ain.Sse64Fx2.src) );
3623 rexAMode_R_enc_enc( vregEnc3210(i->Ain.Sse32FLo.dst),
3624 vregEnc3210(i->Ain.Sse32FLo.src) ));
3626 switch (i->Ain.Sse32FLo.op) {
3642 p = doAMode_R_enc_enc(p, vregEnc3210(i->Ain.Sse32FLo.dst),
3643 vregEnc3210(i->Ain.Sse32FLo.src) );
3652 rexAMode_R_enc_enc( vregEnc3210(i->Ain.Sse64FLo.dst),
3653 vregEnc3210(i->Ain.Sse64FLo.src) ));
3655 switch (i->Ain.Sse64FLo.op) {
3669 p = doAMode_R_enc_enc(p, vregEnc3210(i->Ain.Sse64FLo.dst),
3670 vregEnc3210(i->Ain.Sse64FLo.src) );
3679 rexAMode_R_enc_enc( vregEnc3210(i->Ain.SseReRg.dst),
3680 vregEnc3210(i->Ain.SseReRg.src) ));
3682 switch (i->Ain.SseReRg.op) {
3740 p = doAMode_R_enc_enc(p, vregEnc3210(i->Ain.SseReRg.dst),
3741 vregEnc3210(i->Ain.SseReRg.src) );
3747 *p++ = toUChar(0x70 + (i->Ain.SseCMov.cond ^ 1));
3753 rexAMode_R_enc_enc( vregEnc3210(i->Ain.SseCMov.dst),
3754 vregEnc3210(i->Ain.SseCMov.src) ));
3757 p = doAMode_R_enc_enc(p, vregEnc3210(i->Ain.SseCMov.dst),
3758 vregEnc3210(i->Ain.SseCMov.src) );
3767 rexAMode_R_enc_enc( vregEnc3210(i->Ain.SseShuf.dst),
3768 vregEnc3210(i->Ain.SseShuf.src) ));
3771 p = doAMode_R_enc_enc(p, vregEnc3210(i->Ain.SseShuf.dst),
3772 vregEnc3210(i->Ain.SseShuf.src) );
3773 *p++ = (UChar)(i->Ain.SseShuf.order);
3777 //uu UInt vex = vexAMode_M( dvreg2ireg(i->Ain.AvxLdSt.reg),
3778 //uu i->Ain.AvxLdSt.addr );
3780 //uu *p++ = toUChar(i->Ain.AvxLdSt.isLoad ? 0x10 : 0x11);
3781 //uu p = doAMode_M(p, dvreg2ireg(i->Ain.AvxLdSt.reg), i->Ain.AvxLdSt.addr);
3807 rex = clearWBit(rexAMode_M_enc(1, i->Ain.EvCheck.amCounter));
3810 p = doAMode_M_enc(p, 1, i->Ain.EvCheck.amCounter);
3820 rex = clearWBit(rexAMode_M_enc(4, i->Ain.EvCheck.amFailAddr));
3823 p = doAMode_M_enc(p, 4, i->Ain.EvCheck.amFailAddr);