Cross Reference: /external/vixl/src/aarch64/assembler-aarch64.cc

Lines Matching defs:rt2
947                     const CPURegister& rt2,
949   LoadStorePair(rt, rt2, src, LoadPairOpFor(rt, rt2));
954                     const CPURegister& rt2,
956   LoadStorePair(rt, rt2, dst, StorePairOpFor(rt, rt2));
969                               const CPURegister& rt2,
972   // 'rt' and 'rt2' can only be aliased for stores.
973   VIXL_ASSERT(((op & LoadStorePairLBit) == 0) || !rt.Is(rt2));
974   VIXL_ASSERT(AreSameSizeAndType(rt, rt2));
978   Instr memop = op | Rt(rt) | Rt2(rt2) | RnSP(addr.GetBaseRegister()) |
998                      const CPURegister& rt2,
1000   LoadStorePairNonTemporal(rt, rt2, src, LoadPairNonTemporalOpFor(rt, rt2));
1005                      const CPURegister& rt2,
1007   LoadStorePairNonTemporal(rt, rt2, dst, StorePairNonTemporalOpFor(rt, rt2));
1012                                          const CPURegister& rt2,
1015   VIXL_ASSERT(!rt.Is(rt2));
1016   VIXL_ASSERT(AreSameSizeAndType(rt, rt2));
1023   Emit(op | Rt(rt) | Rt2(rt2) | RnSP(addr.GetBaseRegister()) |
1269                      const Register& rt2,
1271   VIXL_ASSERT(rt.GetSizeInBits() == rt2.GetSizeInBits());
1274   Emit(op | Rs(rs) | Rt(rt) | Rt2(rt2) | RnSP(dst.GetBaseRegister()));
1279                      const Register& rt2,
1281   VIXL_ASSERT(rt.GetSizeInBits() == rt2.GetSizeInBits());
1284   Emit(op | Rs_mask | Rt(rt) | Rt2(rt2) | RnSP(src.GetBaseRegister()));
1334                       const Register& rt2,
1336   VIXL_ASSERT(rt.GetSizeInBits() == rt2.GetSizeInBits());
1339   Emit(op | Rs(rs) | Rt(rt) | Rt2(rt2) | RnSP(dst.GetBaseRegister()));
1344                       const Register& rt2,
1346   VIXL_ASSERT(rt.GetSizeInBits() == rt2.GetSizeInBits());
1349   Emit(op | Rs_mask | Rt(rt) | Rt2(rt2) | RnSP(src.GetBaseRegister()));
4673                                           const CPURegister& rt2) {
4674   VIXL_ASSERT(AreSameSizeAndType(rt, rt2));
4675   USE(rt2);
4694                                          const CPURegister& rt2) {
4696   return static_cast<LoadStorePairOp>(StorePairOpFor(rt, rt2) |
4702     const CPURegister& rt, const CPURegister& rt2) {
4703   VIXL_ASSERT(AreSameSizeAndType(rt, rt2));
4704   USE(rt2);
4723     const CPURegister& rt, const CPURegister& rt2) {
4726       StorePairNonTemporalOpFor(rt, rt2) | LoadStorePairNonTemporalLBit);