Lines Matching refs:imm
43 ** Refactored ARM address-mode static functions (imm(), reg_imm(), imm12_pre(), etc.)
206 uint32_t immediate, uint32_t& rot, uint32_t& imm)
210 imm = immediate;
222 uint32_t ArmToMipsAssembler::imm(uint32_t immediate)
368 // this works with the imm(), reg_imm() methods above, which are directly
1439 // MD00086 pdf says this is: ADDIU rt, rs, imm -- they do not use Rd
1440 void MIPSAssembler::ADDIU(int Rt, int Rs, int16_t imm)
1442 *mPC++ = (addiu_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | (imm & MSK_16);
1453 void MIPSAssembler::SUBIU(int Rt, int Rs, int16_t imm) // really addiu(d, s, -j)
1455 *mPC++ = (addiu_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | ((-imm) & MSK_16);
1527 void MIPSAssembler::SLTI(int Rt, int Rs, int16_t imm)
1529 *mPC++ = (slti_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | (imm & MSK_16);
1539 void MIPSAssembler::SLTIU(int Rt, int Rs, int16_t imm)
1541 *mPC++ = (sltiu_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | (imm & MSK_16);
1557 void MIPSAssembler::ANDI(int Rt, int Rs, uint16_t imm) // todo: support larger immediate
1559 *mPC++ = (andi_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | (imm & MSK_16);
1569 void MIPSAssembler::ORI(int Rt, int Rs, uint16_t imm)
1571 *mPC++ = (ori_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | (imm & MSK_16);
1591 void MIPSAssembler::XORI(int Rt, int Rs, uint16_t imm) // todo: support larger immediate
1593 *mPC++ = (xori_op<<OP_SHF) | (Rt<<RT_SHF) | (Rs<<RS_SHF) | (imm & MSK_16);