/external/swiftshader/third_party/LLVM/include/llvm/MC/ |
H A D | MCInst.h | 97 static MCOperand CreateReg(unsigned Reg) { function in class:llvm::MCOperand
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FunctionLoweringInfo.cpp | 363 /// CreateReg - Allocate a single virtual register for the given type. 364 unsigned FunctionLoweringInfo::CreateReg(MVT VT) { function in class:FunctionLoweringInfo 389 unsigned R = CreateReg(RegisterVT);
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
H A D | FunctionLoweringInfo.cpp | 207 /// CreateReg - Allocate a single virtual register for the given type. 208 unsigned FunctionLoweringInfo::CreateReg(EVT VT) { function in class:FunctionLoweringInfo 230 unsigned R = CreateReg(RegisterVT);
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/AsmParser/ |
H A D | MBlazeAsmParser.cpp | 189 Inst.addOperand(MCOperand::CreateReg(getReg())); 205 Inst.addOperand(MCOperand::CreateReg(getMemBase())); 209 Inst.addOperand(MCOperand::CreateReg(RegOff)); 230 static MBlazeOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { function in struct:__anon18768::MBlazeOperand 405 return MBlazeOperand::CreateReg(RegNo, S, E);
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/external/llvm/lib/Target/Sparc/AsmParser/ |
H A D | SparcAsmParser.cpp | 350 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind, function in class:__anon13141::SparcOperand 787 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E)); 848 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E);
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/external/llvm/lib/Target/X86/AsmParser/ |
H A D | X86Operand.h | 476 CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc, function in struct:llvm::X86Operand
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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
H A D | MachineOperand.h | 489 static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false, function in class:llvm::MachineOperand
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/external/swiftshader/third_party/LLVM/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 297 Inst.addOperand(MCOperand::CreateReg(getReg())); 307 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg())); 309 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg())); 311 Inst.addOperand(MCOperand::CreateReg(getMemSegReg())); 326 static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc) { function in struct:__anon18835::X86Operand 507 return X86Operand::CreateReg(RegNo, Start, End); 795 Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc); 808 Operands.begin()[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
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/external/llvm/lib/Target/AMDGPU/AsmParser/ |
H A D | AMDGPUAsmParser.cpp | 510 static AMDGPUOperand::Ptr CreateReg(unsigned RegNo, SMLoc S, function in class:__anon12860::AMDGPUOperand 963 return AMDGPUOperand::CreateReg(Reg, StartLoc, EndLoc,
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/external/llvm/lib/Target/Hexagon/AsmParser/ |
H A D | HexagonAsmParser.cpp | 584 static std::unique_ptr<HexagonOperand> CreateReg(unsigned RegNum, SMLoc S, function in struct:__anon12949::HexagonOperand 1127 Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End)); 1143 Operands.push_back(HexagonOperand::CreateReg(Register, Begin, End)); 1153 Operands.push_back(HexagonOperand::CreateReg(
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 930 Inst.addOperand(MCOperand::CreateReg(RegNum)); 960 Inst.addOperand(MCOperand::CreateReg(getReg())); 965 Inst.addOperand(MCOperand::CreateReg(getReg())); 971 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); 972 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); 980 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); 996 Inst.addOperand(MCOperand::CreateReg(*I)); 1154 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1159 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1178 Inst.addOperand(MCOperand::CreateReg(Memor 1497 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { function [all...] |
/external/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 1626 CreateReg(unsigned RegNum, bool isVector, SMLoc S, SMLoc E, MCContext &Ctx) { function in class:__anon12830::AArch64Operand 2814 AArch64Operand::CreateReg(Reg, true, S, getLoc(), getContext())); 2863 AArch64Operand::CreateReg(Reg, false, S, getLoc(), getContext())); 3090 AArch64Operand::CreateReg(RegNum, false, S, getLoc(), Ctx)); 3111 AArch64Operand::CreateReg(RegNum, false, S, getLoc(), Ctx)); 3823 Operands[2] = AArch64Operand::CreateReg( 3961 Operands[2] = AArch64Operand::CreateReg(Reg, false, Op.getStartLoc(), 3976 Operands[2] = AArch64Operand::CreateReg(Reg, false, Op.getStartLoc(), 3992 Operands[1] = AArch64Operand::CreateReg(Reg, false, Op.getStartLoc(), 4008 Operands[2] = AArch64Operand::CreateReg(zre [all...] |
/external/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 635 static std::unique_ptr<MipsOperand> CreateReg(unsigned Index, RegKind RegKind, function in class:__anon13062::MipsOperand 1234 return CreateReg(Index, RegKind_Numeric, RegInfo, S, E, Parser); 1242 return CreateReg(Index, RegKind_GPR, RegInfo, S, E, Parser); 1250 return CreateReg(Index, RegKind_FGR, RegInfo, S, E, Parser); 1258 return CreateReg(Index, RegKind_HWRegs, RegInfo, S, E, Parser); 1266 return CreateReg(Index, RegKind_FCC, RegInfo, S, E, Parser); 1274 return CreateReg(Index, RegKind_ACC, RegInfo, S, E, Parser); 1282 return CreateReg(Index, RegKind_MSA128, RegInfo, S, E, Parser); 1290 return CreateReg(Index, RegKind_MSACtrl, RegInfo, S, E, Parser);
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/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 2639 static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S, function 3200 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(), 6054 ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc()); 6075 ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc()));
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