| /external/llvm/lib/Target/BPF/ |
| H A D | BPFInstrInfo.cpp | 47 unsigned SrcReg, bool IsKill, int FI,
56 .addReg(SrcReg, getKillRegState(IsKill))
45 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool IsKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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| /external/llvm/lib/Target/Mips/ |
| H A D | Mips16RegisterInfo.cpp | 126 bool IsKill = false; local
142 IsKill = true;
144 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
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| H A D | MipsSERegisterInfo.cpp | 157 bool IsKill = false; local
192 IsKill = true;
209 IsKill = true;
213 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
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| H A D | MipsSEFrameLowering.cpp | 811 bool IsKill = !IsRAAndRetAddrIsTaken; local
813 TII.storeRegToStackSlot(*EntryBlock, MI, Reg, IsKill,
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| /external/libchrome/sandbox/linux/seccomp-bpf-helpers/ |
| H A D | syscall_sets.cc | 17 bool SyscallSets::IsKill(int sysno) { function in class:sandbox::SyscallSets
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 283 unsigned Dst, unsigned Src, bool IsKill) {
286 .addReg(Src, getKillRegState(IsKill));
282 insertCopy(const TargetInstrInfo *TII, MachineInstr &MI, unsigned Dst, unsigned Src, bool IsKill) argument
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.cpp | 179 bool IsKill = false; local
205 IsKill = true;
208 MI.getOperand(FIOp).ChangeToRegister(BP, false, false, IsKill);
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| H A D | HexagonBlockRanges.cpp | 318 bool IsKill = Op.isKill(); local
321 if (IsKill)
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| H A D | HexagonFrameLowering.cpp | 1089 bool IsKill = !HRI.isEHReturnCalleeSaveReg(Reg); local
1092 HII.storeRegToStackSlot(MBB, MI, Reg, IsKill, FI, RC, &HRI);
1093 if (IsKill)
1404 bool IsKill = MI->getOperand(2).isKill(); local
1415 .addReg(SrcR, getKillRegState(IsKill));
1467 bool IsKill = MI->getOperand(2).isKill(); local
1488 .addReg(SrcR, getKillRegState(IsKill))
1552 bool IsKill = MI->getOperand(2).isKill(); local
1574 .addReg(SrcLo, getKillRegState(IsKill))
1586 .addReg(SrcHi, getKillRegState(IsKill))
1654 bool IsKill = MI->getOperand(2).isKill(); local
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 419 bool IsKill = SrcDst->isKill(); local
473 SrcDstRegState |= getKillRegState(IsKill);
521 bool IsKill = MI->getOperand(0).isKill(); local
523 unsigned SubKillState = getKillRegState((NumSubRegs == 1) && IsKill);
535 .addReg(SubReg, getKillRegState(IsKill))
555 SuperKillState |= getKillRegState(IsKill);
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| /external/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 52 unsigned SourceRegister, bool IsKill, int FrameIndex,
64 .addReg(SourceRegister, getKillRegState(IsKill))
50 storeRegToStackSlot( MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, unsigned SourceRegister, bool IsKill, int FrameIndex, const TargetRegisterClass *RegisterClass, const TargetRegisterInfo *RegisterInfo) const argument
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 826 bool IsKill = MO.isKill(); local
827 if (IsKill)
829 Regs.push_back(std::make_pair(Reg, IsKill));
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| /external/llvm/lib/CodeGen/ |
| H A D | ScheduleDAGInstrs.cpp | 429 bool IsKill = MO.getSubReg() == 0 || MO.isUndef(); local
433 KillLaneMask = IsKill ? ~0u : DefLaneMask;
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