Searched defs:MI (Results 151 - 175 of 629) sorted by relevance

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/external/llvm/include/llvm/Target/
H A DTargetSubtargetInfo.h118 const MachineInstr *MI,
191 /// \brief Enable use of alias analysis during code generation (during MI
117 resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const argument
/external/llvm/lib/CodeGen/AsmPrinter/
H A DDbgValueHistoryCalculator.cpp27 // \brief If @MI is a DBG_VALUE with debug value described by a
30 static unsigned isDescribedByReg(const MachineInstr &MI) { argument
31 assert(MI.isDebugValue());
32 assert(MI.getNumOperands() == 4);
35 return MI.getOperand(0).isReg() ? MI.getOperand(0).getReg() : 0;
39 const MachineInstr &MI) {
42 assert(MI.isDebugValue() && "not a DBG_VALUE");
45 Ranges.back().first->isIdenticalTo(MI)) {
47 << "\t" << Ranges.back().first << "\t" << MI << "\ local
38 startInstrRange(InlinedVariable Var, const MachineInstr &MI) argument
53 endInstrRange(InlinedVariable Var, const MachineInstr &MI) argument
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H A DDebugHandlerBase.cpp54 MCSymbol *DebugHandlerBase::getLabelBeforeInsn(const MachineInstr *MI) { argument
55 MCSymbol *Label = LabelsBeforeInsn.lookup(MI);
61 MCSymbol *DebugHandlerBase::getLabelAfterInsn(const MachineInstr *MI) { argument
62 return LabelsAfterInsn.lookup(MI);
170 void DebugHandlerBase::beginInstruction(const MachineInstr *MI) { argument
175 CurMI = MI;
179 LabelsBeforeInsn.find(MI);
/external/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp109 static bool tryOrrMovk(uint64_t UImm, uint64_t OrrImm, MachineInstr &MI, argument
120 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ORRXri))
121 .addOperand(MI.getOperand(0))
127 const unsigned DstReg = MI.getOperand(0).getReg();
128 const bool DstIsDead = MI.getOperand(0).isDead();
130 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi))
136 transferImpOps(MI, MIB, MIB1);
137 MI.eraseFromParent();
160 static bool tryToreplicateChunks(uint64_t UImm, MachineInstr &MI,
187 BuildMI(MBB, MBBI, MI
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H A DAArch64PBQPRegAlloc.cpp321 const MachineInstr &MI) {
323 SlotIndex SI = LIs.getInstructionIndex(MI);
337 for (const auto &MI: MBB) {
342 if(regJustKilledBefore(LIs, r, MI)) {
344 MI.print(dbgs()););
354 switch (MI.getOpcode()) {
363 unsigned Rd = MI.getOperand(0).getReg();
364 unsigned Ra = MI.getOperand(3).getReg();
373 unsigned Rd = MI.getOperand(0).getReg();
320 regJustKilledBefore(const LiveIntervals &LIs, unsigned reg, const MachineInstr &MI) argument
/external/llvm/lib/Target/AMDGPU/
H A DAMDGPUMCInstLower.cpp49 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { argument
51 int MCOpcode = ST.getInstrInfo()->pseudoToMCOpcode(MI->getOpcode());
54 LLVMContext &C = MI->getParent()->getParent()->getFunction()->getContext();
56 "a target-specific version: " + Twine(MI->getOpcode()));
61 for (const MachineOperand &MO : MI->explicit_operands()) {
98 void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) { argument
103 if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) {
104 LLVMContext &C = MI->getParent()->getParent()->getFunction()->getContext();
106 MI->dump();
109 if (MI
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H A DGCNHazardRecognizer.cpp37 void GCNHazardRecognizer::EmitInstruction(MachineInstr *MI) { argument
38 CurrCycleInstr = MI;
43 MachineInstr *MI = SU->getInstr(); local
45 if (SIInstrInfo::isSMRD(*MI) && checkSMRDHazards(MI) > 0)
48 if (SIInstrInfo::isVMEM(*MI) && checkVMEMHazards(MI) > 0)
51 if (SIInstrInfo::isDPP(*MI) && checkDPPHazards(MI) > 0)
61 unsigned GCNHazardRecognizer::PreEmitNoops(MachineInstr *MI) { argument
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H A DR600ClauseMergePass.cpp34 static bool isCFAlu(const MachineInstr &MI) { argument
35 switch (MI.getOpcode()) {
50 unsigned getCFAluSize(const MachineInstr &MI) const;
51 bool isCFAluEnabled(const MachineInstr &MI) const;
74 unsigned R600ClauseMergePass::getCFAluSize(const MachineInstr &MI) const {
75 assert(isCFAlu(MI));
76 return MI
77 .getOperand(TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::COUNT))
81 bool R600ClauseMergePass::isCFAluEnabled(const MachineInstr &MI) const {
82 assert(isCFAlu(MI));
185 MachineInstr &MI = *I++; local
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H A DR600EmitClauseMarkers.cpp41 unsigned OccupiedDwords(MachineInstr &MI) const {
42 switch (MI.getOpcode()) {
56 if (TII->isLDSRetInstr(MI.getOpcode()))
59 if (TII->isVector(MI) || TII->isCubeOp(MI.getOpcode()) ||
60 TII->isReductionOp(MI.getOpcode()))
64 for (MachineInstr::mop_iterator It = MI.operands_begin(),
65 E = MI.operands_end();
74 bool isALU(const MachineInstr &MI) const {
75 if (TII->isALUInstr(MI
118 SubstituteKCacheBank(MachineInstr &MI, std::vector<std::pair<unsigned, unsigned>> &CachedConsts, bool UpdateInstr = true) const argument
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H A DSIFixSGPRCopies.cpp115 static bool hasVGPROperands(const MachineInstr &MI, const SIRegisterInfo *TRI) { argument
116 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
117 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
118 if (!MI.getOperand(i).isReg() ||
119 !TargetRegisterInfo::isVirtualRegister(MI.getOperand(i).getReg()))
122 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg())))
176 static bool foldVGPRCopyIntoRegSequence(MachineInstr &MI, argument
180 assert(MI.isRegSequence());
182 unsigned DstReg = MI.getOperand(0).getReg();
214 MI
253 MachineInstr &MI = *I; local
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/external/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DSIMCCodeEmitter.cpp54 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
59 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
65 unsigned getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
191 void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, argument
195 uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups, STI);
196 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
207 for (unsigned i = 0, e = MI.getNumOperands(); i < e; ++i) {
217 const MCOperand &Op = MI.getOperand(i);
242 unsigned SIMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo, argument
245 const MCOperand &MO = MI
257 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
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/external/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.cpp93 static void foldFrameOffset(MachineInstr &MI, int &Offset, unsigned DstReg) { argument
94 int Opcode = MI.getOpcode();
103 if (DstReg != MI.getOperand(0).getReg()) {
110 Offset += -MI.getOperand(2).getImm();
113 Offset += MI.getOperand(2).getImm();
118 MI.eraseFromParent();
126 MachineInstr &MI = *II; local
127 DebugLoc dl = MI.getDebugLoc();
128 MachineBasicBlock &MBB = *MI.getParent();
134 int FrameIndex = MI
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/external/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFMCCodeEmitter.cpp44 uint64_t getBinaryCodeForInstr(const MCInst &MI,
50 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
54 uint64_t getMemoryOpValue(const MCInst &MI, unsigned Op,
58 void encodeInstruction(const MCInst &MI, raw_ostream &OS,
76 unsigned BPFMCCodeEmitter::getMachineOpValue(const MCInst &MI, argument
91 if (MI.getOpcode() == BPF::JAL)
94 else if (MI.getOpcode() == BPF::LD_imm64)
108 void BPFMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, argument
111 unsigned Opcode = MI.getOpcode();
116 uint64_t Value = getBinaryCodeForInstr(MI, Fixup
154 getMemoryOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument
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/external/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp105 RegisterRefs(const MachineInstr &MI) : Vector(MI.getNumOperands()) { argument
107 const MachineOperand &MO = MI.getOperand(i);
124 bool HexagonEvaluator::evaluate(const MachineInstr &MI,
130 for (unsigned i = 0, n = MI.getNumOperands(); i < n; ++i) {
131 const MachineOperand &MO = MI.getOperand(i);
141 if (MI.mayLoad())
142 return evaluateLoad(MI, Inputs, Outputs);
158 if (MI.isCopy()) {
159 if (evaluateFormalCopy(MI, Input
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H A DHexagonBranchRelaxation.cpp65 bool isJumpOutOfRange(MachineInstr &MI,
106 for (auto &MI : B.instrs())
107 InstOffset += HII->getSize(&MI);
132 bool HexagonBranchRelaxation::isJumpOutOfRange(MachineInstr &MI, argument
134 MachineBasicBlock &B = *MI.getParent();
158 if (TBB && &MI == &*FirstTerm) {
169 if (&MI != &*SecondTerm)
185 for (auto &MI : B) {
186 if (!MI.isBranch() || !isJumpOutOfRange(MI, BlockToInstOffse
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H A DHexagonMachineFunctionInfo.h50 void addAllocaAdjustInst(MachineInstr* MI) { argument
51 AllocaAdjustInsts.push_back(MI);
60 void setStartPacket(MachineInstr* MI) { argument
61 PacketInfo[MI] |= Hexagon::StartPacket;
63 void setEndPacket(MachineInstr* MI) { argument
64 PacketInfo[MI] |= Hexagon::EndPacket;
66 bool isStartPacket(const MachineInstr* MI) const {
67 return (PacketInfo.count(MI) &&
68 (PacketInfo.find(MI)->second & Hexagon::StartPacket));
70 bool isEndPacket(const MachineInstr* MI) cons
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H A DRDFCopy.cpp29 bool CopyPropagation::interpretAsCopy(const MachineInstr *MI, EqualityMap &EM) { argument
30 unsigned Opc = MI->getOpcode();
33 const MachineOperand &Dst = MI->getOperand(0);
34 const MachineOperand &Src = MI->getOperand(1);
58 const MachineOperand &Dst = MI->getOperand(0);
62 if (!TII.getRegSequenceInputs(*MI, 0, Inputs))
/external/llvm/lib/Target/Lanai/
H A DLanaiAsmPrinter.cpp50 void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
52 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
55 void EmitInstruction(const MachineInstr *MI) override;
60 void customEmitInstruction(const MachineInstr *MI);
61 void emitCallInstruction(const MachineInstr *MI);
65 void LanaiAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, argument
67 const MachineOperand &MO = MI->getOperand(OpNum);
112 bool LanaiAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, argument
125 const MachineOperand &FlagsOP = MI->getOperand(OpNo - 1);
133 if (RegOp >= MI
151 emitCallInstruction(const MachineInstr *MI) argument
191 customEmitInstruction(const MachineInstr *MI) argument
199 EmitInstruction(const MachineInstr *MI) argument
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H A DLanaiDelaySlotFiller.cpp66 void insertDefsUses(MachineBasicBlock::instr_iterator MI,
72 bool delayHasHazard(MachineBasicBlock::instr_iterator MI, bool &SawLoad,
180 bool Filler::delayHasHazard(MachineBasicBlock::instr_iterator MI, bool &SawLoad, argument
183 if (MI->isImplicitDef() || MI->isKill())
188 if (MI->mayLoad()) {
194 if (MI->mayStore()) {
202 assert((!MI->isCall() && !MI->isReturn()) &&
205 for (unsigned I = 0, E = MI
227 insertDefsUses(MachineBasicBlock::instr_iterator MI, SmallSet<unsigned, 32> &RegDefs, SmallSet<unsigned, 32> &RegUses) argument
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H A DLanaiRegisterInfo.cpp140 MachineInstr &MI = *II; local
141 MachineFunction &MF = *MI.getParent()->getParent();
145 DebugLoc DL = MI.getDebugLoc();
147 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
150 MI.getOperand(FIOperandNum + 1).getImm();
169 if ((isSPLSOpcode(MI.getOpcode()) && !isInt<10>(Offset)) ||
187 BuildMI(*MI.getParent(), II, DL, TII->get(Lanai::MOVHI), Reg)
189 BuildMI(*MI.getParent(), II, DL, TII->get(Lanai::OR_I_LO), Reg)
194 BuildMI(*MI.getParent(), II, DL, TII->get(Lanai::ADD_I_LO), Reg)
199 if (MI
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/external/llvm/lib/Target/MSP430/
H A DMSP430FrameLowering.cpp98 MachineInstr *MI = local
102 MI->getOperand(3).setIsDead();
160 MachineInstr *MI = local
165 MI->getOperand(3).setIsDead();
170 MachineInstr *MI = local
174 MI->getOperand(3).setIsDead();
182 MachineBasicBlock::iterator MI,
189 if (MI != MBB.end()) DL = MI->getDebugLoc();
200 BuildMI(MBB, MI, D
181 spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
207 restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
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H A DMSP430InstrInfo.cpp38 MachineBasicBlock::iterator MI,
43 if (MI != MBB.end()) DL = MI->getDebugLoc();
53 BuildMI(MBB, MI, DL, get(MSP430::MOV16mr))
57 BuildMI(MBB, MI, DL, get(MSP430::MOV8mr))
65 MachineBasicBlock::iterator MI,
70 if (MI != MBB.end()) DL = MI->getDebugLoc();
80 BuildMI(MBB, MI, DL, get(MSP430::MOV16rm))
84 BuildMI(MBB, MI, D
37 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
64 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/llvm/lib/Target/Mips/InstPrinter/
H A DMipsInstPrinter.cpp32 static bool isReg(const MCInst &MI, unsigned OpNo) { argument
33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
34 return MI.getOperand(OpNo).getReg() == R;
79 void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O, argument
81 switch (MI->getOpcode()) {
91 printSaveRestore(MI, O);
96 printSaveRestore(MI, O);
101 printSaveRestore(MI, O);
106 printSaveRestore(MI, O);
112 if (!printAliasInstr(MI,
125 printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument
143 printUImm(const MCInst *MI, int opNum, raw_ostream &O) argument
158 printMemOperand(const MCInst *MI, int opNum, raw_ostream &O) argument
185 printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O) argument
195 printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) argument
201 printRegisterPair(const MCInst *MI, int opNum, raw_ostream &O) argument
206 printSHFMask(const MCInst *MI, int opNum, raw_ostream &O) argument
210 printAlias(const char *Str, const MCInst &MI, unsigned OpNo, raw_ostream &OS) argument
217 printAlias(const char *Str, const MCInst &MI, unsigned OpNo0, unsigned OpNo1, raw_ostream &OS) argument
226 printAlias(const MCInst &MI, raw_ostream &OS) argument
274 printSaveRestore(const MCInst *MI, raw_ostream &O) argument
285 printRegisterList(const MCInst *MI, int opNum, raw_ostream &O) argument
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/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp50 bool isIndirectJump(const MCInst &MI) { argument
51 if (MI.getOpcode() == Mips::JALR) {
54 assert(MI.getOperand(0).isReg());
55 return MI.getOperand(0).getReg() == Mips::ZERO;
57 return MI.getOpcode() == Mips::JR;
60 bool isStackPointerFirstOperand(const MCInst &MI) { argument
61 return (MI.getNumOperands() > 0 && MI.getOperand(0).isReg()
62 && MI.getOperand(0).getReg() == Mips::SP);
65 bool isCall(const MCInst &MI, boo argument
105 sandboxIndirectJump(const MCInst &MI, const MCSubtargetInfo &STI) argument
116 sandboxLoadStoreStackChange(const MCInst &MI, unsigned AddrIdx, const MCSubtargetInfo &STI, bool MaskBefore, bool MaskAfter) argument
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/external/llvm/lib/Target/Mips/
H A DMips16FrameLowering.cpp109 MachineBasicBlock::iterator MI,
137 MachineBasicBlock::iterator MI,
108 spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
136 restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument

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