/external/llvm/lib/Target/Lanai/ |
H A D | LanaiMemAluCombiner.cpp | 150 bool isNonVolatileMemoryOp(const MachineInstr &MI) { argument 151 if (!MI.hasOneMemOperand()) 156 if (mergedOpcode(MI.getOpcode(), false) == 0) 159 const MachineMemOperand *MemOperand = *MI.memoperands_begin();
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/external/llvm/lib/Target/Mips/ |
H A D | MipsOptimizePICCall.cpp | 77 /// \brief Test if MI jumps to a function via a register. 82 bool isCallViaRegister(MachineInstr &MI, unsigned &Reg, 103 /// Return the first MachineOperand of MI if it is a used virtual register. 104 static MachineOperand *getCallTargetRegOpnd(MachineInstr &MI) { argument 105 if (MI.getNumOperands() == 0) 108 MachineOperand &MO = MI.getOperand(0); 141 /// Search MI's operands for register GP and erase it. 142 static void eraseGPOpnd(MachineInstr &MI) { argument 146 MachineFunction &MF = *MI.getParent()->getParent(); 147 MVT::SimpleValueType Ty = getRegTy(MI 246 isCallViaRegister(MachineInstr &MI, unsigned &Reg, ValueType &Val) const argument [all...] |
/external/llvm/lib/Target/PowerPC/InstPrinter/ |
H A D | PPCInstPrinter.cpp | 56 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O, argument 59 if (MI->getOpcode() == PPC::RLWINM) { 60 unsigned char SH = MI->getOperand(2).getImm(); 61 unsigned char MB = MI->getOperand(3).getImm(); 62 unsigned char ME = MI->getOperand(4).getImm(); 72 printOperand(MI, 0, O); 74 printOperand(MI, 1, O); 82 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) && 83 MI 145 printPredicateOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, const char *Modifier) argument 242 printU1ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 249 printU2ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 256 printU3ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 263 printU4ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 270 printS5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 277 printU5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 284 printU6ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 291 printU7ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 298 printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 305 printU10ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 312 printU12ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 319 printS16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 327 printU16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 335 printBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 346 printAbsBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 355 printcrbitm(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 373 printMemRegImm(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 384 printMemRegReg(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 397 printTLSCall(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 432 printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCVSXFMAMutate.cpp | 77 MachineInstr *MI = I; local 85 int AltOpc = PPC::getAltVSXFMAOpcode(MI->getOpcode()); 108 SlotIndex FMAIdx = LIS->getInstructionIndex(*MI); 111 LIS->getInterval(MI->getOperand(1).getReg()).Query(FMAIdx).valueIn(); 121 if (!AddendMI || AddendMI->getParent() != MI->getParent()) 185 unsigned OldFMAReg = MI->getOperand(0).getReg(); 189 unsigned Reg2 = MI->getOperand(2).getReg(); 190 unsigned Reg3 = MI->getOperand(3).getReg(); 206 // If the addend copy is used only by this MI, then the addend source 217 unsigned KilledProdReg = MI [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | DelaySlotFiller.cpp | 70 void insertCallDefsUses(MachineBasicBlock::iterator MI, 74 void insertDefsUses(MachineBasicBlock::iterator MI, 115 MachineBasicBlock::iterator MI = I; local 118 // If MI is restore, try combining it with previous inst. 120 (MI->getOpcode() == SP::RESTORErr 121 || MI->getOpcode() == SP::RESTOREri)) { 122 Changed |= tryCombineRestoreWithPrevInst(MBB, MI); 129 (MI->getOpcode() == SP::FCMPS || MI->getOpcode() == SP::FCMPD 130 || MI 292 insertCallDefsUses(MachineBasicBlock::iterator MI, SmallSet<unsigned, 32>& RegDefs, SmallSet<unsigned, 32>& RegUses) argument 321 insertDefsUses(MachineBasicBlock::iterator MI, SmallSet<unsigned, 32>& RegDefs, SmallSet<unsigned, 32>& RegUses) argument [all...] |
H A D | LeonPasses.cpp | 29 int LEONMachineFunctionPass::GetRegIndexForOperand(MachineInstr &MI, argument 31 if (MI.getNumOperands() > 0) { 33 OperandIndex = MI.getNumOperands() - 1; 36 if (MI.getNumOperands() > (unsigned)OperandIndex && 37 MI.getOperand(OperandIndex).isReg()) { 38 return (int)MI.getOperand(OperandIndex).getReg(); 87 MachineInstr &MI = *MBBI; local 88 unsigned Opcode = MI.getOpcode(); 93 } else if (MI.isInlineAsm()) { 96 MI 138 MachineInstr &MI = *MBBI; local 250 MachineInstr &MI = *MBBI; local 363 MachineInstr &MI = *MBBI; local 421 MachineInstr &MI = *MBBI; local 456 MachineInstr &MI = *MBBI; local 520 MachineInstr &MI = *MBBI; local 649 MachineInstr &MI = *MBBI; local 723 MachineInstr &MI = *MBBI; local 762 MachineInstr &MI = *MBBI; local 837 MachineInstr &MI = *MBBI; local [all...] |
H A D | SparcFrameLowering.cpp | 190 MachineInstr &MI = *I; local 191 int Size = MI.getOperand(0).getImm(); 192 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZLongBranch.cpp | 150 TerminatorInfo describeTerminator(MachineInstr &MI); 155 void splitBranchOnCount(MachineInstr *MI, unsigned AddOpcode); 156 void splitCompareBranch(MachineInstr *MI, unsigned CompareOpcode); 212 // Return a description of terminator instruction MI. 213 TerminatorInfo SystemZLongBranch::describeTerminator(MachineInstr &MI) { argument 215 Terminator.Size = TII->getInstSizeInBytes(MI); 216 if (MI.isConditionalBranch() || MI.isUnconditionalBranch()) { 217 switch (MI.getOpcode()) { 254 Terminator.Branch = &MI; 283 MachineBasicBlock::iterator MI = MBB->begin(); local 350 splitBranchOnCount(MachineInstr *MI, unsigned AddOpcode) argument 369 splitCompareBranch(MachineInstr *MI, unsigned CompareOpcode) argument [all...] |
/external/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyAsmPrinter.cpp | 75 void EmitInstruction(const MachineInstr *MI) override; 77 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, 80 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, 220 void WebAssemblyAsmPrinter::EmitInstruction(const MachineInstr *MI) { argument 221 DEBUG(dbgs() << "EmitInstruction: " << *MI << '\n'); 223 switch (MI->getOpcode()) { 237 assert(MFI->isVRegStackified(MI->getOperand(0).getReg())); 242 MFI->getWAReg(MI->getOperand(0).getReg())))); 258 MCInstLowering.Lower(MI, TmpInst); 273 bool WebAssemblyAsmPrinter::PrintAsmOperand(const MachineInstr *MI, argument 312 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &OS) argument [all...] |
H A D | WebAssemblyCFGStackify.cpp | 290 for (MachineInstr &MI : Pred->terminators()) 291 for (MachineOperand &MO : MI.explicit_operands()) 297 /// Test whether MI is a child of some other node in an expression tree. 298 static bool IsChild(const MachineInstr &MI, argument 300 if (MI.getNumOperands() == 0) 302 const MachineOperand &MO = MI.getOperand(0); 478 for (auto &MI : reverse(MBB)) { 479 switch (MI.getOpcode()) { 495 Stack.push_back(LoopTops[&MI]); 498 if (MI [all...] |
/external/llvm/lib/Target/X86/InstPrinter/ |
H A D | X86InstComments.cpp | 174 static MVT getRegOperandVectorVT(const MCInst *MI, const MVT &ScalarVT, argument 176 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); 182 static MVT getZeroExtensionResultType(const MCInst *MI) { argument 183 switch (MI->getOpcode()) { 189 return getRegOperandVectorVT(MI, MVT::i16, 0); 195 return getRegOperandVectorVT(MI, MVT::i32, 0); 203 return getRegOperandVectorVT(MI, MVT::i64, 0); 208 static std::string getMaskName(const MCInst *MI, const char *DestName, argument 215 switch (MI->getOpcode()) { 281 MaskRegName = getRegName(MI 368 EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, const char *(*getRegName)(unsigned)) argument [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86AsmPrinter.cpp | 170 static void printOperand(X86AsmPrinter &P, const MachineInstr *MI, 177 static void printPCRelImm(X86AsmPrinter &P, const MachineInstr *MI, argument 179 const MachineOperand &MO = MI->getOperand(OpNo); 184 printOperand(P, MI, OpNo, O); 195 static void printOperand(X86AsmPrinter &P, const MachineInstr *MI, argument 198 const MachineOperand &MO = MI->getOperand(OpNo); 228 static void printLeaMemReference(X86AsmPrinter &P, const MachineInstr *MI, argument 231 const MachineOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg); 232 const MachineOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg); 233 const MachineOperand &DispSpec = MI 280 printMemReference(X86AsmPrinter &P, const MachineInstr *MI, unsigned Op, raw_ostream &O, const char *Modifier = nullptr) argument 292 printIntelMemReference(X86AsmPrinter &P, const MachineInstr *MI, unsigned Op, raw_ostream &O, const char *Modifier = nullptr, unsigned AsmVariant = 1) argument 374 PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument 465 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument [all...] |
H A D | X86CallFrameOptimization.cpp | 99 MachineBasicBlock::iterator MI, 152 for (MachineInstr &MI : BB) { 153 if (MI.getOpcode() == FrameSetupOpcode) { 157 } else if (MI.getOpcode() == FrameDestroyOpcode) { 238 for (auto &MI : MBB) 239 if (MI.getOpcode() == FrameSetupOpcode) { 241 collectCallInfo(MF, MBB, MI, Context); 260 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 262 if (MI == MBB.end()) 266 int Opcode = MI 259 classifyInstruction( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const X86RegisterInfo &RegInfo, DenseSet<unsigned int> &UsedRegs) argument [all...] |
H A D | X86ExpandPseudo.cpp | 73 MachineInstr &MI = *MBBI; local 74 unsigned Opcode = MI.getOpcode();
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H A D | X86FixupLEAs.cpp | 113 MachineInstr &MI = *MBBI; local 114 switch (MI.getOpcode()) { 117 const MachineOperand &Src = MI.getOperand(1); 118 const MachineOperand &Dest = MI.getOperand(0); 120 BuildMI(*MF, MI.getDebugLoc(), 121 TII->get(MI.getOpcode() == X86::MOV32rr ? X86::LEA32r 144 if (!MI.getOperand(2).isImm()) { 152 if (MI.getOperand(1).getReg() != MI.getOperand(2).getReg()) { 159 return TII->convertToThreeAddress(MFI, MI, nullpt 190 MachineInstr &MI = *I; local 267 MachineInstr &MI = *I; local 302 MachineInstr &MI = *I; local 339 MachineInstr &MI = *I; local [all...] |
H A D | X86InstrBuilder.h | 88 static inline X86AddressMode getAddressFromInstr(MachineInstr *MI, argument 91 MachineOperand &Op = MI->getOperand(Operand); 99 Op = MI->getOperand(Operand + 1); 102 Op = MI->getOperand(Operand + 2); 105 Op = MI->getOperand(Operand + 3); 178 MachineInstr *MI = MIB; local 179 MachineFunction &MF = *MI->getParent()->getParent(); 181 const MCInstrDesc &MCID = MI->getDesc();
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H A D | X86InstrInfo.h | 121 inline static bool isLeaMem(const MachineInstr &MI, unsigned Op) { argument 122 if (MI.getOperand(Op).isFI()) 124 return Op + X86::AddrSegmentReg <= MI.getNumOperands() && 125 MI.getOperand(Op + X86::AddrBaseReg).isReg() && 126 isScale(MI.getOperand(Op + X86::AddrScaleAmt)) && 127 MI.getOperand(Op + X86::AddrIndexReg).isReg() && 128 (MI.getOperand(Op + X86::AddrDisp).isImm() || 129 MI.getOperand(Op + X86::AddrDisp).isGlobal() || 130 MI.getOperand(Op + X86::AddrDisp).isCPI() || 131 MI 134 isMem(const MachineInstr &MI, unsigned Op) argument [all...] |
H A D | X86RegisterInfo.cpp | 578 MachineInstr &MI = *II; local 579 MachineFunction &MF = *MI.getParent()->getParent(); 581 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 584 unsigned Opc = MI.getOpcode(); 604 MachineOperand &FI = MI.getOperand(FIOperandNum); 619 MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false); 637 int64_t Offset = MI.getOperand(FIOperandNum + 1).getImm() + FIOffset; 638 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); 642 if (MI.getOperand(FIOperandNum+3).isImm()) { 644 int Imm = (int)(MI [all...] |
H A D | X86VZeroUpper.cpp | 130 static bool hasYmmReg(MachineInstr &MI) { argument 131 for (const MachineOperand &MO : MI.operands()) { 132 if (MI.isCall() && MO.isRegMask() && !clobbersAllYmmRegs(MO)) 145 static bool callClobbersAnyYmmReg(MachineInstr &MI) { argument 146 assert(MI.isCall() && "Can only be called on call instructions."); 147 for (const MachineOperand &MO : MI.operands()) { 184 for (MachineInstr &MI : MBB) { 187 bool IsReturnFromX86INTR = IsX86INTR && MI.isReturn(); 188 bool IsControlFlow = MI.isCall() || MI [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreAsmPrinter.cpp | 65 void printInlineJT(const MachineInstr *MI, int opNum, raw_ostream &O, 67 void printInlineJT32(const MachineInstr *MI, int opNum, raw_ostream &O) { argument 68 printInlineJT(MI, opNum, O, ".jmptable32"); 70 void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O); 71 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, 74 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, 82 void EmitInstruction(const MachineInstr *MI) override; 192 printInlineJT(const MachineInstr *MI, int opNum, raw_ostream &O, argument 194 unsigned JTI = MI->getOperand(opNum).getIndex(); 195 const MachineFunction *MF = MI 208 printOperand(const MachineInstr *MI, int opNum, raw_ostream &O) argument 239 PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, unsigned AsmVariant,const char *ExtraCode, raw_ostream &O) argument 253 PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, unsigned AsmVariant, const char *ExtraCode, raw_ostream &O) argument 266 EmitInstruction(const MachineInstr *MI) argument [all...] |
H A D | XCoreInstrInfo.cpp | 63 unsigned XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, argument 65 int Opcode = MI.getOpcode(); 68 if ((MI.getOperand(1).isFI()) && // is a stack slot 69 (MI.getOperand(2).isImm()) && // the imm is zero 70 (isZeroImm(MI.getOperand(2)))) { 71 FrameIndex = MI.getOperand(1).getIndex(); 72 return MI.getOperand(0).getReg(); 83 unsigned XCoreInstrInfo::isStoreToStackSlot(const MachineInstr &MI, argument 85 int Opcode = MI.getOpcode(); 88 if ((MI 425 loadImmediate( MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned Reg, uint64_t Value) const argument [all...] |
H A D | XCoreRegisterInfo.cpp | 65 MachineInstr &MI = *II; local 66 MachineBasicBlock &MBB = *MI.getParent(); 67 DebugLoc dl = MI.getDebugLoc(); 69 switch (MI.getOpcode()) { 74 .addMemOperand(*MI.memoperands_begin()); 78 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) 81 .addMemOperand(*MI.memoperands_begin()); 98 MachineInstr &MI = *II; local 99 MachineBasicBlock &MBB = *MI.getParent(); 100 DebugLoc dl = MI 132 MachineInstr &MI = *II; local 166 MachineInstr &MI = *II; local 265 MachineInstr &MI = *II; local [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDGPUInstrInfo.cpp | 36 bool AMDGPUInstrInfo::isCoalescableExtInstr(const MachineInstr &MI, argument 43 unsigned AMDGPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, argument 49 unsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, argument 55 bool AMDGPUInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI, argument 61 unsigned AMDGPUInstrInfo::isStoreFromStackSlot(const MachineInstr *MI, argument 66 unsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE(const MachineInstr *MI, argument 71 bool AMDGPUInstrInfo::hasStoreFromStackSlot(const MachineInstr *MI, argument 123 MachineBasicBlock::iterator MI, 133 MachineBasicBlock::iterator MI, 142 MachineInstr *MI, 122 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 132 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 141 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl<unsigned> &Ops, int FrameIndex) const argument 149 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl<unsigned> &Ops, MachineInstr *LoadMI) const argument 157 canFoldMemoryOperand(const MachineInstr *MI, const SmallVectorImpl<unsigned> &Ops) const argument 164 unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl<MachineInstr*> &NewMIs) const argument 221 DefinesPredicate(MachineInstr *MI, std::vector<MachineOperand> &Pred) const argument 238 convertToISA(MachineInstr & MI, MachineFunction &MF, DebugLoc DL) const argument [all...] |
H A D | R600ISelLowering.cpp | 54 MachineInstr * MI, MachineBasicBlock * BB) const 58 MachineBasicBlock::iterator I = *MI; 60 switch (MI->getOpcode()) { 61 default: return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); 66 .addOperand(MI->getOperand(0)) 67 .addOperand(MI->getOperand(1)) 77 .addOperand(MI->getOperand(0)) 78 .addOperand(MI->getOperand(1)) 89 .addOperand(MI->getOperand(0)) 90 .addOperand(MI 53 EmitInstrWithCustomInserter( MachineInstr * MI, MachineBasicBlock * BB) const argument [all...] |
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | SIMCCodeEmitter.cpp | 74 virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS, 78 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 84 unsigned GPRAlign(const MCInst &MI, unsigned OpNo, unsigned shift) const; 87 virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo, 91 virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo, 96 virtual uint64_t i32LiteralEncode(const MCInst &MI, unsigned OpNo, 100 virtual uint32_t SMRDmemriEncode(const MCInst &MI, unsigned OpNo, 104 virtual uint64_t VOPPostEncode(const MCInst &MI, uint64_t Value) const; 109 unsigned getEncodingType(const MCInst &MI) const; 112 unsigned getEncodingBytes(const MCInst &MI) cons 131 EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups) const argument 140 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups) const argument 161 GPRAlign(const MCInst &MI, unsigned OpNo, unsigned shift) const argument 167 GPR2AlignEncode(const MCInst &MI, unsigned OpNo , SmallVectorImpl<MCFixup> &Fixup) const argument 173 GPR4AlignEncode(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixup) const argument 179 i32LiteralEncode(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixup) const argument 197 SMRDmemriEncode(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixup) const argument 219 VOPPostEncode(const MCInst &MI, uint64_t Value) const argument [all...] |