Searched defs:MI (Results 51 - 75 of 629) sorted by relevance

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/external/llvm/lib/Target/WebAssembly/
H A DWebAssemblyPrepareForLiveIntervals.cpp62 static bool IsArgument(const MachineInstr *MI) { argument
63 switch (MI->getOpcode()) {
125 MachineInstr *MI = &*MII++; local
126 if (IsArgument(MI)) {
127 MI->removeFromParent();
128 Entry.insert(Entry.begin(), MI);
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDGPUCodeEmitter.h21 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
22 virtual uint64_t getMachineOpValue(const MachineInstr &MI, argument
24 virtual unsigned GPR4AlignEncode(const MachineInstr &MI, argument
28 virtual unsigned GPR2AlignEncode(const MachineInstr &MI, argument
32 virtual uint64_t VOPPostEncode(const MachineInstr &MI, argument
36 virtual uint64_t i32LiteralEncode(const MachineInstr &MI, argument
40 virtual uint32_t SMRDmemriEncode(const MachineInstr &MI, unsigned OpNo) argument
H A DAMDGPUConvertToISA.cpp57 MachineInstr &MI = *I; local
58 TII->convertToISA(MI, MF, MBB.findDebugLoc(I));
H A DAMDGPUMCInstLower.cpp30 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { argument
31 OutMI.setOpcode(MI->getOpcode());
33 for (unsigned i = 0, e = MI->getNumExplicitOperands(); i != e; ++i) {
34 const MachineOperand &MO = MI->getOperand(i);
58 void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) { argument
62 if (MI->getOpcode() == AMDGPU::MASK_WRITE) {
66 if (MI->isBundle()) {
67 const MachineBasicBlock *MBB = MI->getParent();
68 MachineBasicBlock::const_instr_iterator I = MI;
79 MCInstLowering.lower(MI, TmpIns
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H A DAMDGPURegisterInfo.cpp38 void AMDGPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, argument
H A DSIInstrInfo.cpp38 MachineBasicBlock::iterator MI, DebugLoc DL,
48 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
55 MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::V_MOV_IMM_I32), DebugLoc()); local
56 MachineInstrBuilder(MI).addReg(DstReg, RegState::Define);
57 MachineInstrBuilder(MI).addImm(Imm);
59 return MI;
37 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
H A DAMDGPUMCCodeEmitter.h28 uint64_t getBinaryCodeForInstr(const MCInst &MI,
31 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, argument
36 virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo, argument
40 virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo, argument
44 virtual uint64_t VOPPostEncode(const MCInst &MI, uint64_t Value) const { argument
47 virtual uint64_t i32LiteralEncode(const MCInst &MI, unsigned OpNo, argument
51 virtual uint32_t SMRDmemriEncode(const MCInst &MI, unsigned OpNo, argument
/external/swiftshader/third_party/LLVM/include/llvm/ADT/
H A DUniqueVector.h55 typename std::map<T, unsigned>::const_iterator MI = Map.find(Entry); local
58 if (MI != Map.end()) return MI->second;
/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DExpandISelPseudos.cpp62 MachineInstr *MI = MBBI++; local
64 // If MI is a pseudo, expand it.
65 const MCInstrDesc &MCID = MI->getDesc();
69 TLI->EmitInstrWithCustomInserter(MI, MBB);
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DARMMCInstLower.cpp114 void llvm::LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, argument
116 OutMI.setOpcode(MI->getOpcode());
118 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
119 const MachineOperand &MO = MI->getOperand(i);
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
H A DSPUAsmPrinter.cpp51 void printInstruction(const MachineInstr *MI, raw_ostream &OS);
55 void EmitInstruction(const MachineInstr *MI) { argument
58 printInstruction(MI, OS);
63 void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { argument
64 const MachineOperand &MO = MI->getOperand(OpNo);
74 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
77 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
83 printU7ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) argument
85 unsigned int value = MI->getOperand(OpNo).getImm();
91 printShufAddr(const MachineInstr *MI, unsigne
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/InstPrinter/
H A DMBlazeInstPrinter.cpp28 void MBlazeInstPrinter::printInst(const MCInst *MI, raw_ostream &O, argument
30 printInstruction(MI, O);
34 void MBlazeInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, argument
37 const MCOperand &Op = MI->getOperand(OpNo);
48 void MBlazeInstPrinter::printFSLImm(const MCInst *MI, int OpNo, argument
50 const MCOperand &MO = MI->getOperand(OpNo);
54 printOperand(MI, OpNo, O, NULL);
57 void MBlazeInstPrinter::printUnsignedImm(const MCInst *MI, int OpNo, argument
59 const MCOperand &MO = MI->getOperand(OpNo);
63 printOperand(MI, OpN
66 printMemOperand(const MCInst *MI, int OpNo, raw_ostream &O, const char *Modifier) argument
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/external/swiftshader/third_party/LLVM/lib/Target/MSP430/InstPrinter/
H A DMSP430InstPrinter.cpp28 void MSP430InstPrinter::printInst(const MCInst *MI, raw_ostream &O, argument
30 printInstruction(MI, O);
34 void MSP430InstPrinter::printPCRelImmOperand(const MCInst *MI, unsigned OpNo, argument
36 const MCOperand &Op = MI->getOperand(OpNo);
45 void MSP430InstPrinter::printOperand(const MCInst *MI, unsigned OpNo, argument
48 const MCOperand &Op = MI->getOperand(OpNo);
59 void MSP430InstPrinter::printSrcMemOperand(const MCInst *MI, unsigned OpNo, argument
62 const MCOperand &Base = MI->getOperand(OpNo);
63 const MCOperand &Disp = MI->getOperand(OpNo+1);
88 void MSP430InstPrinter::printCCOperand(const MCInst *MI, unsigne argument
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/external/swiftshader/third_party/LLVM/lib/Target/MSP430/
H A DMSP430MCInstLower.cpp109 void MSP430MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { argument
110 OutMI.setOpcode(MI->getOpcode());
112 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
113 const MachineOperand &MO = MI->getOperand(i);
118 MI->dump();
/external/swiftshader/third_party/LLVM/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp42 void EncodeInstruction(const MCInst &MI, raw_ostream &OS, argument
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
H A DMipsMCInstLower.cpp116 void MipsMCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { argument
117 OutMI.setOpcode(MI->getOpcode());
119 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
120 const MachineOperand &MO = MI->getOperand(i);
/external/libcxx/test/std/iterators/predef.iterators/move.iterators/move.iter.ops/move.iter.op.star/
H A Dop_star.pass.cpp67 typedef std::move_iterator<const char *> MI; typedef
68 constexpr MI it1 = std::make_move_iterator(p);
69 constexpr MI it2 = std::make_move_iterator(p+1);
/external/llvm/include/llvm/ADT/
H A DUniqueVector.h61 typename std::map<T, unsigned>::const_iterator MI = Map.find(Entry); local
64 if (MI != Map.end()) return MI->second;
/external/llvm/include/llvm/CodeGen/
H A DMachineInstrBundleIterator.h31 MachineInstrBundleIterator(instr_iterator MI) : MII(MI) {} argument
33 MachineInstrBundleIterator(Ty &MI) : MII(MI) { argument
34 assert(!MI.isBundledWithPred() && "It's not legal to initialize "
36 "bundled MI");
38 MachineInstrBundleIterator(Ty *MI) : MII(MI) { argument
40 assert((!MI || !MI
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/external/llvm/lib/CodeGen/AsmPrinter/
H A DDebugHandlerBase.h71 /// Ensure that a label will be emitted before MI.
72 void requestLabelBeforeInsn(const MachineInstr *MI) { argument
73 LabelsBeforeInsn.insert(std::make_pair(MI, nullptr));
76 /// Ensure that a label will be emitted after MI.
77 void requestLabelAfterInsn(const MachineInstr *MI) { argument
78 LabelsAfterInsn.insert(std::make_pair(MI, nullptr));
83 void beginInstruction(const MachineInstr *MI) override;
90 MCSymbol *getLabelBeforeInsn(const MachineInstr *MI);
93 MCSymbol *getLabelAfterInsn(const MachineInstr *MI);
/external/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp28 this->MI = nullptr;
38 void MachineIRBuilder::setInstr(MachineInstr &MI, bool Before) { argument
39 assert(MI.getParent() && "Instruction is not part of a basic block");
40 setMBB(*MI.getParent());
41 this->MI = &MI;
46 if (MI) {
48 return MI;
49 if (!MI->getNextNode())
51 return MI
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/external/llvm/lib/CodeGen/
H A DRegAllocBase.cpp112 MachineInstr *MI = nullptr; local
118 MI = TmpMI;
122 if (MI)
123 MI->emitError("inline assembly requires more registers than available");
H A DRegUsageInfoPropagate.cpp64 static void setRegMask(MachineInstr &MI, const uint32_t *RegMask) { argument
65 for (MachineOperand &MO : MI.operands()) {
101 for (MachineInstr &MI : MBB) {
102 if (!MI.isCall())
106 DEBUG(dbgs() << MI << "\n");
112 setRegMask(MI, &(*RegMask)[0]);
116 MachineOperand &Operand = MI.getOperand(0);
124 DEBUG(dbgs() << MI << "\n");
H A DStackMapLivenessAnalysis.cpp78 void addLiveOutSetToMI(MachineFunction &MF, MachineInstr &MI);
154 MachineInstr &MI) {
157 MI.addOperand(MF, MO);
153 addLiveOutSetToMI(MachineFunction &MF, MachineInstr &MI) argument
/external/llvm/lib/Target/AArch64/
H A DAArch64DeadRegisterDefinitionsPass.cpp39 bool implicitlyDefinesOverlappingReg(unsigned Reg, const MachineInstr &MI);
41 bool usesFrameIndex(const MachineInstr &MI);
70 unsigned Reg, const MachineInstr &MI) {
71 for (const MachineOperand &MO : MI.implicit_operands())
78 bool AArch64DeadRegisterDefinitions::usesFrameIndex(const MachineInstr &MI) { argument
79 for (const MachineOperand &Op : MI.uses())
88 for (MachineInstr &MI : MBB) {
89 if (usesFrameIndex(MI)) {
96 if (MI.definesRegister(AArch64::XZR) || MI
69 implicitlyDefinesOverlappingReg( unsigned Reg, const MachineInstr &MI) argument
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