/external/vixl/tools/test_generator/ |
H A D | data_types.py | 31 or C++ `Operand` and `MemOperand` objects are operands. We can think of them 35 to represent it (e.g. "Register", "ShiftType", "MemOperand", ...) and a name 129 corresponds to C++ objects such as `Operand` or `MemOperand`. 371 code = "__ Ldr({name}, MemOperand(input_ptr, offsetof(Inputs, {name})));" 375 code = "__ Str({name}, MemOperand(result_ptr, offsetof(Inputs, {name})));" 400 __ Ldr(nzcv_bits, MemOperand(input_ptr, offsetof(Inputs, {}))); 414 __ Str(nzcv_bits, MemOperand(result_ptr, offsetof(Inputs, {}))); 440 __ Ldr(q_bit, MemOperand(input_ptr, offsetof(Inputs, {}))); 454 __ Str(q_bit, MemOperand(result_ptr, offsetof(Inputs, {}))); 474 __ Ldr(ge_bits, MemOperand(input_pt 493 class MemOperand(Input): class in inherits:Input [all...] |
/external/llvm/lib/Target/Lanai/ |
H A D | LanaiMemAluCombiner.cpp | 159 const MachineMemOperand *MemOperand = *MI.memoperands_begin(); local 162 if (MemOperand->isVolatile())
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/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCCodeEmitter.cpp | 121 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 126 int MemOperand, const MCInst &MI, 129 void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 387 int MemOperand, const MCInst &MI, 593 EmitSegmentOverridePrefix(TSFlags, CurByte, MemOperand, MI, OS); 716 unsigned &CurByte, int MemOperand, 723 if (MemOperand != -1) { // If the instruction has a memory operand. 724 switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) { 747 /// MemOperand is the operand # of the start of a memory operand if present. If 750 int MemOperand, cons 715 EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, const MCInst &MI, raw_ostream &OS) const argument 749 EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, const MCInst &MI, const MCInstrDesc &Desc, raw_ostream &OS) const argument [all...] |
/external/vixl/src/aarch32/ |
H A D | operands-aarch32.h | 612 // MemOperand represents the addressing mode of a load or store instruction. 614 // Usage: <instr> <Rt> , <MemOperand> 618 // <MemOperand> is the rest of the arguments to the instruction 620 // <MemOperand> can be in one of 3 addressing modes: 647 class MemOperand { class in namespace:vixl::aarch32 651 explicit MemOperand(Register rn, AddrMode addrmode = Offset) function in class:vixl::aarch32::MemOperand 668 MemOperand(Register rn, int32_t offset, AddrMode addrmode = Offset) function in class:vixl::aarch32::MemOperand 678 MemOperand(Register rn, Sign sign, int32_t offset, AddrMode addrmode = Offset) function in class:vixl::aarch32::MemOperand 695 MemOperand(Register rn, Sign sign, Register rm, AddrMode addrmode = Offset) function in class:vixl::aarch32::MemOperand 709 MemOperand(Registe function in class:vixl::aarch32::MemOperand 725 MemOperand(Register rn, function in class:vixl::aarch32::MemOperand 745 MemOperand(Register rn, Register rm, Shift shift, AddrMode addrmode = Offset) function in class:vixl::aarch32::MemOperand 763 MemOperand(Register rn, function in class:vixl::aarch32::MemOperand 785 MemOperand(Register rn, function in class:vixl::aarch32::MemOperand [all...] |
/external/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCCodeEmitter.cpp | 134 void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 141 bool emitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, 146 int MemOperand, const MCInstrDesc &Desc) const; 597 int MemOperand, const MCInst &MI, 720 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); 722 unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg); 766 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); 768 unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand+X86::AddrIndexReg); 798 unsigned BaseRegEnc = getX86RegEncoding(MI, MemOperand + X86::AddrBaseReg); 800 unsigned IndexRegEnc = getX86RegEncoding(MI, MemOperand 596 EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, const MCInst &MI, const MCInstrDesc &Desc, raw_ostream &OS) const argument 958 DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags, int MemOperand, const MCInstrDesc &Desc) const argument 1057 emitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, const MCInst &MI, const MCInstrDesc &Desc, const MCSubtargetInfo &STI, raw_ostream &OS) const argument [all...] |
/external/v8/src/arm64/ |
H A D | assembler-arm64.h | 635 // MemOperand represents a memory operand in a load or store instruction. 636 class MemOperand { class in namespace:v8::internal 638 inline MemOperand(); 639 inline explicit MemOperand(Register base, 642 inline explicit MemOperand(Register base, 646 inline explicit MemOperand(Register base, 650 inline explicit MemOperand(Register base, 675 // Check if two MemOperand are consistent for stp/ldp use. 676 static PairResult AreConsistentForPair(const MemOperand& operandA, 677 const MemOperand [all...] |
/external/v8/src/ia32/ |
H A D | macro-assembler-ia32.h | 34 typedef Operand MemOperand; typedef in namespace:v8::internal
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/external/v8/src/x64/ |
H A D | macro-assembler-x64.h | 45 typedef Operand MemOperand; typedef in namespace:v8::internal
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/external/v8/src/x87/ |
H A D | macro-assembler-x87.h | 37 typedef Operand MemOperand; typedef in namespace:v8::internal
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/external/v8/src/arm/ |
H A D | assembler-arm.cc | 366 // Implementation of Operand and MemOperand 415 MemOperand::MemOperand(Register rn, int32_t offset, AddrMode am) { function in class:v8::internal::MemOperand 430 MemOperand::MemOperand(Register rn, Register rm, AddrMode am) { function in class:v8::internal::MemOperand 439 MemOperand::MemOperand(Register rn, Register rm, function in class:v8::internal::MemOperand 513 // str(r, MemOperand(sp, 4, NegPreIndex), al) instruction (aka push(r)) 517 // ldr(r, MemOperand(sp, 4, PostIndex), al) instruction (aka pop(r)) 1288 ldr(rd, MemOperand(p [all...] |
/external/v8/src/mips/ |
H A D | assembler-mips.cc | 219 // Implementation of Operand and MemOperand. 238 MemOperand::MemOperand(Register rm, int32_t offset) : Operand(rm) { function in class:v8::internal::MemOperand 243 MemOperand::MemOperand(Register rm, int32_t unit, int32_t multiplier, function in class:v8::internal::MemOperand 262 // sw(r, MemOperand(sp, 0)) 265 // lw(r, MemOperand(sp, 0)) 1780 void Assembler::LoadRegPlusOffsetToAt(const MemOperand& src) { 1791 int32_t Assembler::LoadRegPlusUpperOffsetPartToAt(const MemOperand& src) { 1807 int32_t Assembler::LoadUpperOffsetForTwoMemoryAccesses(const MemOperand [all...] |
/external/v8/src/ppc/ |
H A D | assembler-ppc.cc | 187 // Implementation of Operand and MemOperand 206 MemOperand::MemOperand(Register rn, int32_t offset) { function in class:v8::internal::MemOperand 213 MemOperand::MemOperand(Register ra, Register rb) { function in class:v8::internal::MemOperand 1117 void Assembler::lbz(Register dst, const MemOperand& src) { 1123 void Assembler::lbzx(Register rt, const MemOperand& src) { 1132 void Assembler::lbzux(Register rt, const MemOperand& src) { 1141 void Assembler::lhz(Register dst, const MemOperand& src) { 1147 void Assembler::lhzx(Register rt, const MemOperand [all...] |
/external/v8/src/mips64/ |
H A D | assembler-mips64.cc | 198 // Implementation of Operand and MemOperand. 217 MemOperand::MemOperand(Register rm, int32_t offset) : Operand(rm) { function in class:v8::internal::MemOperand 222 MemOperand::MemOperand(Register rm, int32_t unit, int32_t multiplier, function in class:v8::internal::MemOperand 242 // sd(r, MemOperand(sp, 0)) 245 // ld(r, MemOperand(sp, 0)) 1940 void Assembler::LoadRegPlusOffsetToAt(const MemOperand& src) { 1950 void Assembler::lb(Register rd, const MemOperand& rs) { 1955 GenInstrImmediate(LB, at, rd, 0); // Equiv to lb(rd, MemOperand(a [all...] |
/external/v8/src/s390/ |
H A D | assembler-s390.cc | 248 // Implementation of Operand and MemOperand 266 MemOperand::MemOperand(Register rn, int32_t offset) { function in class:v8::internal::MemOperand 272 MemOperand::MemOperand(Register rx, Register rb, int32_t offset) { function in class:v8::internal::MemOperand 534 void Assembler::stm(Register r1, Register r2, const MemOperand& src) { 539 void Assembler::stmy(Register r1, Register r2, const MemOperand& src) { 544 void Assembler::stmg(Register r1, Register r2, const MemOperand& src) { 621 void Assembler::name(Register r, const MemOperand& opnd) { \ 797 void Assembler::name(Register r1, Register r3, const MemOperand [all...] |