Searched defs:Opcode (Results 1 - 25 of 323) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/
H A DPPCPredicates.cpp19 PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) { argument
20 switch (Opcode) {
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCPredicates.cpp19 PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) { argument
20 switch (Opcode) {
53 PPC::Predicate PPC::getSwappedPredicate(PPC::Predicate Opcode) { argument
54 switch (Opcode) {
/external/llvm/include/llvm/Target/
H A DTargetOpcodes.h29 /// Check whether the given Opcode is a generic opcode that is not supposed
31 static inline bool isPreISelGenericOpcode(unsigned Opcode) { argument
32 return Opcode >= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_START &&
33 Opcode <= TargetOpcode::PRE_ISEL_GENERIC_OPCODE_END;
/external/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.h24 static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) { argument
25 switch (Opcode) {
H A DARMHazardRecognizer.cpp26 unsigned Opcode = MCID.getOpcode(); local
27 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DARMSelectionDAGInfo.h23 static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) { argument
24 switch (Opcode) {
H A DARMHazardRecognizer.cpp26 unsigned Opcode = MCID.getOpcode(); local
27 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
85 unsigned Opcode = MI->getOpcode(); local
88 } else if (Opcode == ARM::t2IT) {
/external/llvm/include/llvm/MC/
H A DMCInstBuilder.h27 MCInstBuilder(unsigned Opcode) { argument
28 Inst.setOpcode(Opcode);
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMUnwindOpAsm.h74 void EmitInt8(unsigned Opcode) { argument
75 Ops.push_back(Opcode & 0xff);
79 void EmitInt16(unsigned Opcode) { argument
80 Ops.push_back((Opcode >> 8) & 0xff);
81 Ops.push_back(Opcode & 0xff);
85 void EmitBytes(const uint8_t *Opcode, size_t Size) { argument
86 Ops.insert(Ops.end(), Opcode, Opcode + Size);
/external/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.h141 static inline bool isSPLSOpcode(unsigned Opcode) { argument
142 switch (Opcode) {
155 static inline bool isRMOpcode(unsigned Opcode) { argument
156 switch (Opcode) {
165 static inline bool isRRMOpcode(unsigned Opcode) { argument
166 switch (Opcode) {
H A DLanaiTargetTransformInfo.h59 unsigned Opcode, Type *Ty,
64 int ISD = TLI->InstructionOpcodeToISD(Opcode);
68 return BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
79 return 64 * BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
58 getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue, TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue, TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None, TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None) argument
/external/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h340 inline bool isPCREL(unsigned Opcode) { argument
341 return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET;
402 const char *getTargetNodeName(unsigned Opcode) const override;
499 SelectionDAG &DAG, unsigned Opcode,
525 unsigned Opcode) const;
585 unsigned Opcode) const;
587 unsigned Opcode) const;
590 unsigned Opcode, bool NoFloat) const;
593 unsigned Opcode) cons
[all...]
H A DSystemZTargetTransformInfo.cpp66 int SystemZTTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx, argument
79 switch (Opcode) {
H A DSystemZRegisterInfo.cpp93 unsigned Opcode = MI->getOpcode(); local
94 unsigned OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
110 OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
/external/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp59 MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, Type *Ty) { argument
60 MachineInstr *NewMI = BuildMI(getMF(), DL, getTII().get(Opcode));
62 assert(isPreISelGenericOpcode(Opcode) &&
66 assert(!isPreISelGenericOpcode(Opcode) &&
72 MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, unsigned Res, argument
74 return buildInstr(Opcode, nullptr, Res, Op0, Op1);
77 MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, Type *Ty, argument
80 MachineInstr *NewMI = buildInstr(Opcode, Ty);
88 MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, unsigned Res, argument
90 MachineInstr *NewMI = buildInstr(Opcode, nullpt
95 buildInstr(unsigned Opcode) argument
99 buildInstr(unsigned Opcode, Type *Ty, MachineBasicBlock &BB) argument
[all...]
H A DIRTranslator.cpp64 bool IRTranslator::translateBinaryOp(unsigned Opcode, const Instruction &Inst) { argument
72 MIRBuilder.buildInstr(Opcode, Inst.getType(), Res, Op0, Op1);
115 llvm_unreachable("Opcode not supported");
/external/llvm/lib/Target/NVPTX/
H A DNVPTXTargetTransformInfo.cpp93 unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,
99 int ISD = TLI->InstructionOpcodeToISD(Opcode);
103 return BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
116 return BaseT::getArithmeticInstrCost(Opcode, Ty, Opd1Info, Opd2Info,
92 getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info, TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo, TTI::OperandValueProperties Opd2PropInfo) argument
/external/llvm/lib/Target/WebAssembly/
H A DWebAssemblyTargetTransformInfo.cpp47 unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,
52 Opcode, Ty, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo);
55 switch (Opcode) {
66 getArithmeticInstrCost(Opcode, VTy->getElementType()) +
74 unsigned WebAssemblyTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val, argument
76 unsigned Cost = BasicTTIImplBase::getVectorInstrCost(Opcode, Val, Index);
46 getArithmeticInstrCost( unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info, TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo, TTI::OperandValueProperties Opd2PropInfo) argument
/external/clang/include/clang/Analysis/Analyses/
H A DThreadSafetyLogical.h24 enum Opcode { enum in class:clang::threadSafety::lexpr::LExpr
30 Opcode kind() const { return Kind; }
37 LExpr(Opcode Kind) : Kind(Kind) {}
40 Opcode Kind;
59 BinOp(LExpr *LHS, LExpr *RHS, Opcode Code) : LExpr(Code), LHS(LHS), RHS(RHS) {}
/external/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstrInfo.cpp62 int AMDGPUInstrInfo::getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const { argument
64 default: return Opcode;
65 case 1: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_1);
66 case 2: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_2);
67 case 3: return AMDGPU::getMaskedMIMGOp(Opcode, AMDGPU::Channels_3);
82 static int getMCOpcode(uint16_t Opcode, unsigned Gen) { argument
83 return getMCOpcodeGen(Opcode, static_cast<Subtarget>(Gen));
107 int AMDGPUInstrInfo::pseudoToMCOpcode(int Opcode) const {
108 int MCOp = AMDGPU::getMCOpcode(Opcode, subtargetEncodingFamily(ST));
110 // -1 means that Opcode i
[all...]
/external/llvm/lib/Target/BPF/
H A DBPFISelDAGToDAG.cpp119 unsigned Opcode = Node->getOpcode(); local
131 switch (Opcode) {
/external/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyMCTargetDesc.h97 inline unsigned GetDefaultP2Align(unsigned Opcode) { argument
98 switch (Opcode) {
/external/llvm/lib/Target/X86/
H A DX86FixupSetCC.cpp71 bool X86FixupSetCCPass::isSetCCr(unsigned Opcode) { argument
72 switch (Opcode) {
/external/mesa3d/src/gallium/drivers/radeon/
H A DR600ExpandSpecialInstrs.cpp133 unsigned Opcode; local
137 Opcode = AMDGPU::CUBE_r600_real;
140 Opcode = AMDGPU::CUBE_eg_real;
144 Opcode = 0;
148 Opcode = MI.getOpcode();
151 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(Opcode), DstReg)
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp66 PPCHazardRecognizer970::GetInstrType(unsigned Opcode, argument
70 if ((int)Opcode >= 0) {
74 Opcode = ~Opcode;
76 const MCInstrDesc &MCID = TII.get(Opcode);
134 unsigned Opcode = Node->getMachineOpcode(); local
166 if (HasCTRSet && (Opcode == PPC::BCTRL_Darwin || Opcode == PPC::BCTRL_SVR4))
173 switch (Opcode) {
233 unsigned Opcode local
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