/external/llvm/lib/Target/XCore/ |
H A D | XCoreMachineFunctionInfo.cpp | 38 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; local 42 LRSpillSlot = MFI->CreateFixedObject(RC->getSize(), 0, true); 44 LRSpillSlot = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true); 54 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; local 56 FPSpillSlot = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true); 65 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; local 67 EHSpillSlot[0] = MFI->CreateStackObject(RC->getSize(), RC [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
H A D | SPURegisterInfo.h | 54 virtual unsigned getRegPressureLimit( const TargetRegisterClass *RC, argument 95 const TargetRegisterClass *RC,
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/external/llvm/lib/CodeGen/ |
H A D | LiveStackAnalysis.cpp | 58 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { argument 66 S2RCMap.insert(std::make_pair(Slot, RC)); 70 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC); 82 const TargetRegisterClass *RC = getIntervalRegClass(Slot); local 83 if (RC) 84 OS << " [" << TRI->getRegClassName(RC) << "]\n";
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H A D | AggressiveAntiDepBreaker.h | 43 const TargetRegisterClass *RC; member in struct:llvm::AggressiveAntiDepState::__anon12517
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H A D | RegisterClassInfo.cpp | 76 /// compute - Compute the preferred allocation order for RC with reserved 79 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const { 80 assert(RC && "no register class given"); 81 RCInfo &RCI = RegClass[RC->getID()]; 84 unsigned NumRegs = RC->getNumRegs(); 97 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF); 133 // Check if RC is a proper sub-class. 135 TRI->getLargestLegalSuperClass(RC, *MF)) 136 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) 143 dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") 157 const TargetRegisterClass *RC = nullptr; local [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsMachineFunction.cpp | 41 const TargetRegisterClass *RC = local 53 return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC); 58 const TargetRegisterClass *RC = local 63 EhDataRegFI[I] = MF.getFrameInfo()->CreateStackObject(RC->getSize(), 64 RC->getAlignment(), false); 73 const TargetRegisterClass *RC = &Mips::GPR32RegClass; local 77 RC->getSize(), RC->getAlignment(), false); 96 int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) { argument 99 RC [all...] |
/external/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyReplacePhysRegs.cpp | 83 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PReg); local 89 VReg = MRI.createVirtualRegister(RC);
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H A D | WebAssemblyRegColoring.cpp | 139 const TargetRegisterClass *RC = MRI->getRegClass(Old); local 145 if (MRI->getRegClass(SortedIntervals[C]->reg) != RC)
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | AllocationOrder.cpp | 29 const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg); local 45 TRI.getRawAllocationOrder(RC, HintPair.first, Hint, 65 ArrayRef<unsigned> O = RCI.getOrder(RC); 72 !RC->contains(Hint) || RCI.isReserved(Hint)))
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H A D | LiveStackAnalysis.cpp | 55 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { argument 61 S2RCMap.insert(std::make_pair(Slot, RC)); 65 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC); 77 const TargetRegisterClass *RC = getIntervalRegClass(Slot); local 78 if (RC) 79 OS << " [" << RC->getName() << "]\n";
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H A D | AggressiveAntiDepBreaker.h | 44 /// RC - The register class 45 const TargetRegisterClass *RC; member in struct:llvm::AggressiveAntiDepState::__anon18507
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/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
H A D | BlackfinFrameLowering.cpp | 122 const TargetRegisterClass *RC = BF::DPRegisterClass; local 126 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 127 RC->getAlignment(),
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/external/llvm/lib/CodeGen/GlobalISel/ |
H A D | RegisterBank.cpp | 29 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); local 31 if (!covers(RC)) 37 // RegisterBankInfo to find the subclasses of RC, to make sure 42 if (!RC.hasSubClassEq(&SubRC)) 55 bool RegisterBank::covers(const TargetRegisterClass &RC) const { 57 return ContainedRegClasses.test(RC.getID()); 97 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); local 99 if (!covers(RC)) 104 OS << TRI->getRegClassName(&RC);
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXRegisterInfo.cpp | 29 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) { argument 30 if (RC == &NVPTX::Float32RegsRegClass) { 33 if (RC == &NVPTX::Float64RegsRegClass) { 35 } else if (RC == &NVPTX::Int64RegsRegClass) { 37 } else if (RC == &NVPTX::Int32RegsRegClass) { 39 } else if (RC == &NVPTX::Int16RegsRegClass) { 41 } else if (RC == &NVPTX::Int1RegsRegClass) { 43 } else if (RC == &NVPTX::SpecialRegsRegClass) { 51 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) { argument 52 if (RC [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
H A D | Thumb1InstrInfo.cpp | 48 const TargetRegisterClass *RC, 50 assert((RC == ARM::tGPRRegisterClass || 54 if (RC == ARM::tGPRRegisterClass || 77 const TargetRegisterClass *RC, 79 assert((RC == ARM::tGPRRegisterClass || 83 if (RC == ARM::tGPRRegisterClass || 46 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 75 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/llvm/lib/Target/AMDGPU/ |
H A D | SILowerI1Copies.cpp | 86 const TargetRegisterClass *RC = MRI.getRegClass(Reg); local 87 if (RC == &AMDGPU::VReg_1RegClass)
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/external/llvm/lib/Target/ARM/ |
H A D | Thumb1InstrInfo.cpp | 73 const TargetRegisterClass *RC, 75 assert((RC == &ARM::tGPRRegClass || 79 if (RC == &ARM::tGPRRegClass || 99 const TargetRegisterClass *RC, 101 assert((RC == &ARM::tGPRRegClass || 105 if (RC == &ARM::tGPRRegClass || 71 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 97 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/llvm/lib/Target/BPF/ |
H A D | BPFInstrInfo.cpp | 48 const TargetRegisterClass *RC, 54 if (RC == &BPF::GPRRegClass) 66 const TargetRegisterClass *RC, 72 if (RC == &BPF::GPRRegClass) 45 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool IsKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 63 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCVSXCopy.cpp | 56 bool IsRegInClass(unsigned Reg, const TargetRegisterClass *RC, argument 59 return RC->hasSubClassEq(MRI.getRegClass(Reg)); 60 } else if (RC->contains(Reg)) {
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/external/llvm/lib/Target/X86/ |
H A D | X86FixupSetCC.cpp | 160 const TargetRegisterClass *RC = MF.getSubtarget<X86Subtarget>().is64Bit() local 163 unsigned ZeroReg = MRI->createVirtualRegister(RC); 164 unsigned InsertReg = MRI->createVirtualRegister(RC);
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/external/llvm/utils/TableGen/ |
H A D | FastISelEmitter.cpp | 37 const CodeGenRegisterClass *RC; member in struct:__anon13766::InstructionMemo 257 const CodeGenRegisterClass *RC = nullptr; 261 RC = &Target.getRegisterClass(OpLeafRec); 263 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec); 265 RC = OrigDstRC; 270 if (!RC) 276 if (DstRC != RC && !DstRC->hasSubClass(RC)) 279 DstRC = RC; 667 OS << "&" << InstNS << Memo.RC [all...] |
/external/mdnsresponder/mDNSWindows/Java/ |
H A D | makefile | 40 RC = rc macro 142 $(RC) /fo $@ $?
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/external/swiftshader/third_party/LLVM/lib/Target/ |
H A D | TargetRegisterInfo.cpp | 62 const TargetRegisterClass* RC = *I; local 63 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) && 64 (!BestRC || BestRC->hasSubClass(RC))) 65 BestRC = RC; 75 const TargetRegisterClass *RC, BitVector &R){ 76 ArrayRef<unsigned> Order = RC->getRawAllocationOrder(MF); 82 const TargetRegisterClass *RC) const { 84 if (RC) { 85 getAllocatableSetForRC(MF, RC, Allocatabl 74 getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R) argument [all...] |
/external/autotest/client/site_tests/firmware_TouchMTB/ |
H A D | firmware_constants.py | 208 RC = _RobotControl() variable 209 RC.PAUSE_TYPE = 'pause_type' 210 RC.PROMPT = 'finger_control_prompt' 214 RC.PER_GESTURE = 'per_gesture' 218 RC.PER_VARIATION = 'per_variation'
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/external/llvm/include/llvm/CodeGen/ |
H A D | RegisterClassInfo.h | 66 // Compute all information about RC. 67 void compute(const TargetRegisterClass *RC) const; 69 // Return an up-to-date RCInfo for RC. 70 const RCInfo &get(const TargetRegisterClass *RC) const { 71 const RCInfo &RCI = RegClass[RC->getID()]; 73 compute(RC); 85 /// registers in RC in the current function. 86 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { 87 return get(RC).NumRegs; 90 /// getOrder - Returns the preferred allocation order for RC 119 getMinCost(const TargetRegisterClass *RC) argument 127 getLastCostChange(const TargetRegisterClass *RC) argument [all...] |