/external/llvm/lib/Target/AArch64/ |
H A D | AArch64PBQPRegAlloc.cpp | 159 bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, argument 161 if (Rd == Ra) 166 if (TRI->isPhysicalRegister(Rd) || TRI->isPhysicalRegister(Ra)) { 167 DEBUG(dbgs() << "Rd is a physical reg:" << TRI->isPhysicalRegister(Rd) 174 PBQPRAGraph::NodeId node1 = G.getMetadata().getNodeIdForVReg(Rd); 187 const LiveInterval &ld = LIs.getInterval(Rd); 243 void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, argument 249 if (Rd != Ra) { 251 << PrintReg(Rd, TR 363 unsigned Rd = MI.getOperand(0).getReg(); local 373 unsigned Rd = MI.getOperand(0).getReg(); local [all...] |
/external/mesa3d/src/mesa/swrast/ |
H A D | s_blend.c | 489 const GLfloat Rd = dest[i][RCOMP]; local 511 sR = Rd; 516 sR = 1.0F - Rd; 673 dR = Rd; 678 dR = 1.0F - Rd; 743 r = Rs * sR + Rd * dR; 749 r = Rs * sR - Rd * dR; 755 r = Rd * dR - Rs * sR; 761 r = MIN2( Rd, Rs ); 766 r = MAX2( Rd, R [all...] |
/external/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64Disassembler.cpp | 652 unsigned Rd = fieldFromInstruction(Insn, 0, 5); local 657 DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder); 660 DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); 743 unsigned Rd = fieldFromInstruction(insn, 0, 5); local 771 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 792 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 805 unsigned Rd = fieldFromInstruction(insn, 0, 5); local 817 DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); 822 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); 1296 unsigned Rd local 1353 unsigned Rd = fieldFromInstruction(insn, 0, 5); local 1384 unsigned Rd = fieldFromInstruction(insn, 0, 5); local 1423 unsigned Rd = fieldFromInstruction(insn, 0, 5); local 1440 unsigned Rd = fieldFromInstruction(insn, 0, 5); local 1459 unsigned Rd = fieldFromInstruction(insn, 0, 5); local [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 1789 unsigned Rd = fieldFromInstruction32(Insn, 8, 4); local 1798 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1800 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1813 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local 1821 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1823 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 1839 unsigned Rd = fieldFromInstruction32(Insn, 16, 4); local 1848 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1959 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local 1960 Rd | 2208 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local 2458 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local 2497 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local 2533 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local 2568 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local 2621 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local 2666 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local 2709 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local 3260 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local 3392 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local 3451 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local 3509 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local 3576 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local 3640 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local 3710 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local 3774 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local 3848 unsigned Rd = fieldFromInstruction32(Insn, 12, 4); local [all...] |
/external/vixl/src/aarch64/ |
H A D | assembler-aarch64.h | 2583 static Instr Rd(CPURegister rd) { function in class:vixl::aarch64::Assembler
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/external/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 1844 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 1852 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2070 unsigned Rd = fieldFromInstruction(Insn, 8, 4); local 2079 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2081 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2094 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 2102 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2105 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2121 unsigned Rd = fieldFromInstruction(Insn, 16, 4); local 2130 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Addres 2334 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 2659 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 2930 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 2977 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 3025 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 3060 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 3113 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 3158 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 3201 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 4252 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 4382 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 4449 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 4515 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 4582 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 4646 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 4716 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 4780 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local 4861 unsigned Rd = fieldFromInstruction(Insn, 12, 4); local [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonFrameLowering.cpp | 115 // Rd = ALLOCA Rs, A 117 // Rd - address of the allocated space 2187 // Rd = alloca Rs, #A 2189 // If Rs and Rd are different registers, use this sequence: 2190 // Rd = sub(r29, Rs) 2192 // Rd = and(Rd, #-A) ; if necessary 2194 // Rd = add(Rd, #CF) ; CF size aligned to at most A 2196 // Rd 2203 unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg(); local [all...] |
H A D | HexagonInstrInfo.cpp | 1238 unsigned Rd = Op0.getReg(); local 1246 if (Rd != Rs) 1247 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd) 1248 .addReg(Pu, (Rd == Rt) ? K1 : 0) 1250 if (Rd != Rt) 1251 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd) 3340 // Rd = Rs 3347 // Rd = #u6 3377 // Rd=#U6 ; jump #r9:2 3378 // Rd [all...] |
/external/llvm/lib/Target/Hexagon/AsmParser/ |
H A D | HexagonAsmParser.cpp | 1903 MCOperand &Rd = Inst.getOperand(0); local 1926 TmpInst.addOperand(Rd); 1940 if (Value == 0) { // convert to $Rd = $Rs 1942 MCOperand &Rd = Inst.getOperand(0); local 1944 TmpInst.addOperand(Rd); 1952 MCOperand &Rd = Inst.getOperand(0); local 1954 TmpInst.addOperand(Rd); 2150 MCOperand &Rd = Inst.getOperand(0); local 2153 TmpInst.addOperand(Rd);
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