| /external/fec/ |
| H A D | encode_rs_8.c | 12 static enum {UNKNOWN=0,MMX,SSE,SSE2,ALTIVEC,PORT} cpu_mode; enumerator in enum:__anon6367
28 if(f & (1<<26)){ /* SSE2 is present */
29 cpu_mode = SSE2;
60 case SSE2:
|
| H A D | fec.h | 261 extern enum cpu_mode {UNKNOWN=0,PORT,MMX,SSE,SSE2,ALTIVEC} Cpu_mode; enumerator in enum:cpu_mode
|
| /external/skia/src/core/ |
| H A D | SkCpu.h | 16 SSE2 = 1 << 1, enumerator in enum:SkCpu::__anon16941
65 features |= SSE2;
|
| /external/swiftshader/src/Common/ |
| H A D | CPUID.hpp | 53 static bool SSE2; member in class:sw::CPUID
104 return SSE2 && enableSSE2;
|
| H A D | CPUID.cpp | 35 bool CPUID::SSE2 = detectSSE2(); member in class:sw::CPUID
199 return SSE2 = (registers[3] & 0x04000000) != 0;
|
| /external/libchrome/base/ |
| H A D | cpu.h | 23 SSE2, enumerator in enum:base::CPU::IntelMicroArchitecture
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| H A D | X86Subtarget.h | 45 NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42 enumerator in enum:llvm::X86Subtarget::X86SSEEnum
56 /// X86SSELevel - MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or
174 bool hasSSE2() const { return X86SSELevel >= SSE2; }
|
| /external/llvm/lib/Target/X86/ |
| H A D | X86Subtarget.h | 49 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F enumerator in enum:llvm::final::X86SSEEnum
68 /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
383 bool hasSSE2() const { return X86SSELevel >= SSE2; }
457 /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
|
| /external/clang/lib/CodeGen/ |
| H A D | CGBuiltin.cpp | 6767 SSE2, enumerator in enum:X86Features
6799 .Case("sse2", X86Features::SSE2)
|