| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZElimCompare.cpp | 407 unsigned SrcReg2 = local
412 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI)))
455 // Clear any intervening kills of SrcReg and SrcReg2.
459 if (SrcReg2)
460 MBBI->clearRegisterKills(SrcReg2, TRI);
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| H A D | SystemZInstrInfo.cpp | 433 unsigned &SrcReg2, int &Mask,
440 SrcReg2 = 0;
515 MachineInstr &Compare, unsigned SrcReg, unsigned SrcReg2, int Mask,
517 assert(!SrcReg2 && "Only optimizing constant comparisons so far");
432 analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const argument
514 optimizeCompareInstr( MachineInstr &Compare, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const argument
|
| /external/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 180 unsigned &SrcReg2, int &CmpMask,
188 SrcReg2 = 0;
194 SrcReg2 = MI.getOperand(1).getReg();
208 unsigned SrcReg2, int ImmValue,
213 OI->getOperand(2).getReg() == SrcReg2) ||
214 (OI->getOperand(1).getReg() == SrcReg2 &&
286 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask,
306 if (SrcReg2 != 0)
332 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
384 if (SrcReg2 !
179 analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const argument
207 isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg, unsigned SrcReg2, int ImmValue, MachineInstr *OI) argument
285 optimizeCompareInstr( MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const argument
[all...] |
| /external/llvm/lib/CodeGen/ |
| H A D | PeepholeOptimizer.cpp | 565 unsigned SrcReg, SrcReg2; local
567 if (!TII->analyzeCompare(*MI, SrcReg, SrcReg2, CmpMask, CmpValue) ||
569 (SrcReg2 != 0 && TargetRegisterInfo::isPhysicalRegister(SrcReg2)))
573 if (TII->optimizeCompareInstr(*MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| H A D | radeon_program_alu.c | 83 struct rc_src_register SrcReg2)
95 fpi->U.I.SrcReg[2] = SrcReg2;
78 emit3( struct radeon_compiler * c, struct rc_instruction * after, rc_opcode Opcode, struct rc_sub_instruction * base, struct rc_dst_register DstReg, struct rc_src_register SrcReg0, struct rc_src_register SrcReg1, struct rc_src_register SrcReg2) argument
|
| /external/llvm/include/llvm/Target/ |
| H A D | TargetInstrInfo.h | 1162 /// in SrcReg and SrcReg2 if having two register operands, and the value it
1166 unsigned &SrcReg2, int &Mask, int &Value) const {
1174 unsigned SrcReg2, int Mask, int Value,
1165 analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const argument
1173 optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int Mask, int Value, const MachineRegisterInfo *MRI) const argument
|
| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 876 unsigned SrcReg2 = 0; local
878 SrcReg2 = getRegForValue(SrcValue2);
879 if (SrcReg2 == 0)
891 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt))
893 SrcReg2 = ExtReg;
899 .addReg(SrcReg1).addReg(SrcReg2);
1262 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); local
1263 if (SrcReg2 == 0) return false;
1267 std::swap(SrcReg1, SrcReg2);
1270 .addReg(SrcReg1).addReg(SrcReg2);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 690 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
693 unsigned &SrcReg2, int &CmpMask,
712 SrcReg2 = MI.getOperand(2).getReg();
721 SrcReg2 = 0;
731 SrcReg2 = 0;
883 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask,
913 if (CmpValue != 0 || SrcReg2 != 0)
3294 unsigned SrcReg2 = Root.getOperand(IdxOtherOpd).getReg(); local
3303 if (TargetRegisterInfo::isVirtualRegister(SrcReg2))
3304 MRI.constrainRegClass(SrcReg2, R
882 optimizeCompareInstr( MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const argument
[all...] |
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 1425 unsigned SrcReg2 = 0; local
1427 SrcReg2 = getRegForValue(Src2Value);
1428 if (SrcReg2 == 0) return false;
1436 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1437 if (SrcReg2 == 0) return false;
1444 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1);
1446 .addReg(SrcReg1).addReg(SrcReg2));
1763 unsigned SrcReg2 local
[all...] |
| H A D | ARMBaseInstrInfo.cpp | 2284 /// in SrcReg and SrcReg2 if having two register operands, and the value it
2288 unsigned &SrcReg2, int &CmpMask,
2295 SrcReg2 = 0;
2302 SrcReg2 = MI.getOperand(1).getReg();
2309 SrcReg2 = 0;
2362 unsigned SrcReg2, int ImmValue,
2369 OI->getOperand(2).getReg() == SrcReg2) ||
2370 (OI->getOperand(1).getReg() == SrcReg2 &&
2392 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask,
2430 if (SrcReg2 !
2287 analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const argument
2361 isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg, unsigned SrcReg2, int ImmValue, MachineInstr *OI) argument
2391 optimizeCompareInstr( MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const argument
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 1520 /// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
1524 unsigned &SrcReg2, int &Mask,
1585 SrcReg2 = MI.getOperand(2).getReg();
1600 SrcReg2 = 0;
1523 analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const argument
|
| /external/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 2928 unsigned SrcReg2; local
2931 SrcReg2, isKill2, isUndef2, ImplicitOp2))
2941 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2948 LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
4828 unsigned &SrcReg2, int &CmpMask,
4840 SrcReg2 = 0;
4850 SrcReg2 = 0;
4859 SrcReg2 = MI.getOperand(2).getReg();
4871 SrcReg2 = 0;
4880 SrcReg2
4827 analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &CmpMask, int &CmpValue) const argument
4906 isRedundantFlagInstr(MachineInstr &FlagI, unsigned SrcReg, unsigned SrcReg2, int ImmValue, MachineInstr &OI) argument
5044 optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask, int CmpValue, const MachineRegisterInfo *MRI) const argument
[all...] |