Searched defs:SubIdx (Results 1 - 25 of 43) sorted by relevance

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/external/llvm/lib/MC/
H A DMCRegisterInfo.cpp18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, argument
21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
/external/llvm/lib/CodeGen/
H A DTargetRegisterInfo.cpp46 unsigned SubIdx) {
47 return Printable([Reg, TRI, SubIdx](raw_ostream &OS) {
58 if (SubIdx) {
60 OS << ':' << TRI->getSubRegIndexName(SubIdx);
62 OS << ":sub(" << SubIdx << ')'; local
45 PrintReg(unsigned Reg, const TargetRegisterInfo *TRI, unsigned SubIdx) argument
H A DExpandPostRAPseudos.cpp89 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
90 unsigned SubIdx = MI->getOperand(3).getImm(); local
92 assert(SubIdx != 0 && "Invalid index for insert_subreg");
93 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
115 MI->RemoveOperand(3); // SubIdx
H A DMachineCopyPropagation.cpp139 unsigned SubIdx = TRI->getSubRegIndex(PreviousSrc, Src); local
140 return SubIdx == TRI->getSubRegIndex(PreviousDef, Def);
H A DDetectDeadLanes.cpp245 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); local
246 return TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes);
249 unsigned SubIdx = MI.getOperand(3).getImm(); local
251 TRI->reverseComposeSubRegIndexLaneMask(SubIdx, UsedLanes);
260 MO1UsedLanes = UsedLanes & ~TRI->getSubRegIndexLaneMask(SubIdx);
269 unsigned SubIdx = MI.getOperand(2).getImm(); local
270 return TRI->composeSubRegIndexLaneMask(SubIdx, UsedLanes);
319 unsigned SubIdx = MI.getOperand(OpNum + 1).getImm(); local
320 DefinedLanes = TRI->composeSubRegIndexLaneMask(SubIdx, DefinedLanes);
321 DefinedLanes &= TRI->getSubRegIndexLaneMask(SubIdx);
325 unsigned SubIdx = MI.getOperand(3).getImm(); local
337 unsigned SubIdx = MI.getOperand(2).getImm(); local
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DThumb2RegisterInfo.cpp38 unsigned DestReg, unsigned SubIdx,
49 .addReg(DestReg, getDefRegState(true), SubIdx)
35 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
H A DThumb1RegisterInfo.cpp67 unsigned DestReg, unsigned SubIdx,
78 .addReg(DestReg, getDefRegState(true), SubIdx)
64 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
H A DARMBaseRegisterInfo.cpp154 unsigned SubIdx) const {
155 switch (SubIdx) {
802 unsigned DestReg, unsigned SubIdx, int Val,
812 .addReg(DestReg, getDefRegState(true), SubIdx)
799 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
/external/llvm/lib/Target/AMDGPU/
H A DSIMachineFunctionInfo.cpp187 unsigned SubIdx) {
197 Offset += SubIdx * 4;
184 getSpilledReg( MachineFunction *MF, unsigned FrameIndex, unsigned SubIdx) argument
/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DExpandPostRAPseudos.cpp109 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
110 unsigned SubIdx = MI->getOperand(3).getImm(); local
112 assert(SubIdx != 0 && "Invalid index for insert_subreg");
113 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
129 MI->RemoveOperand(3); // SubIdx
H A DRegisterCoalescer.h42 unsigned SubIdx; member in class:llvm::CoalescerPair
60 : TII(tii), TRI(tri), DstReg(0), SrcReg(0), SubIdx(0),
68 /// because DstReg is a physical register, or SubIdx is set.
99 unsigned getSubIdx() const { return SubIdx; }
H A DPeepholeOptimizer.cpp134 unsigned SrcReg, DstReg, SubIdx; local
135 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
246 .addReg(DstReg, 0, SubIdx);
H A DTargetInstrInfoImpl.cpp204 unsigned SubIdx,
208 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
201 reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig, const TargetRegisterInfo &TRI) const argument
H A DLiveDebugVariables.cpp250 /// renameRegister - Update locations to rewrite OldReg as NewReg:SubIdx.
251 void renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx,
337 /// renameRegister - Replace all references to OldReg with NewReg:SubIdx.
338 void renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx);
701 renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx, argument
711 Loc.substVirtReg(NewReg, SubIdx, *TRI);
717 renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx) { argument
727 UV->renameRegister(OldReg, NewReg, SubIdx, TRI);
733 renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx) { argument
735 static_cast<LDVImpl*>(pImpl)->renameRegister(OldReg, NewReg, SubIdx);
[all...]
H A DMachineInstr.cpp117 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, argument
120 if (SubIdx && getSubReg())
121 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
123 if (SubIdx)
124 setSubReg(SubIdx);
1134 unsigned SubIdx,
1137 if (SubIdx)
1138 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1150 MO.substVirtReg(ToReg, SubIdx, RegInf
1132 substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx, const TargetRegisterInfo &RegInfo) argument
[all...]
H A DMachineVerifier.cpp735 unsigned SubIdx = MO->getSubReg(); local
738 if (SubIdx) {
752 if (SubIdx) {
754 TRI->getSubClassWithSubReg(RC, SubIdx);
758 << " does not support subreg index " << SubIdx << "\n";
764 << " does not fully support subreg index " << SubIdx << "\n";
769 if (SubIdx) {
776 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
H A DTwoAddressInstructionPass.cpp1257 unsigned SubIdx = mi->getOperand(3).getImm(); local
1260 mi->getOperand(0).setSubReg(SubIdx);
1290 unsigned DstReg, unsigned SubIdx,
1297 MO.substVirtReg(DstReg, SubIdx, TRI);
1455 unsigned SubIdx = MI->getOperand(i+1).getImm(); local
1477 MRI->getRegClass(SrcReg), SubIdx)) {
1506 .addReg(DstReg, RegState::Define, SubIdx)
1518 unsigned SubIdx = MI->getOperand(i+1).getImm(); local
1519 UpdateRegSequenceSrcs(SrcReg, DstReg, SubIdx, MRI, *TRI);
1289 UpdateRegSequenceSrcs(unsigned SrcReg, unsigned DstReg, unsigned SubIdx, MachineRegisterInfo *MRI, const TargetRegisterInfo &TRI) argument
/external/swiftshader/third_party/LLVM/lib/Target/
H A DTargetRegisterInfo.cpp43 if (SubIdx) {
45 OS << ':' << TRI->getSubRegIndexName(SubIdx);
47 OS << ":sub(" << SubIdx << ')'; local
/external/llvm/lib/Target/ARM/
H A DThumbRegisterInfo.cpp65 unsigned SubIdx, int Val,
77 .addReg(DestReg, getDefRegState(true), SubIdx)
85 unsigned SubIdx, int Val,
96 .addReg(DestReg, getDefRegState(true), SubIdx)
105 const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val,
112 return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred,
115 return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred,
62 emitThumb1LoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) argument
82 emitThumb2LoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) argument
103 emitLoadConstPool( MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
H A DARMBaseRegisterInfo.cpp413 const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val,
423 .addReg(DestReg, getDefRegState(true), SubIdx)
411 emitLoadConstPool( MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
/external/swiftshader/third_party/LLVM/utils/TableGen/
H A DCodeGenRegisters.h152 // registers have a SubIdx sub-register.
153 CodeGenRegisterClass *getSubClassWithSubReg(Record *SubIdx) const {
154 return SubClassWithSubReg.lookup(SubIdx);
157 void setSubClassWithSubReg(Record *SubIdx, CodeGenRegisterClass *SubRC) { argument
158 SubClassWithSubReg[SubIdx] = SubRC;
H A DCodeGenRegisters.cpp771 Record *SubIdx = SubRegIndices[sri]; local
772 SubReg2SetMap::const_iterator I = SRSets.find(SubIdx);
778 RC.setSubClassWithSubReg(SubIdx, &RC);
786 RC.setSubClassWithSubReg(SubIdx, FoundI->second);
795 RC.setSubClassWithSubReg(SubIdx, NewRC);
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp251 unsigned &SubIdx) const {
258 SubIdx = PPC::sub_32;
752 unsigned SubIdx = 0; local
758 SubIdx = PPC::sub_eq; SwapOps = false; break;
762 SubIdx = PPC::sub_eq; SwapOps = true; break;
766 SubIdx = PPC::sub_lt; SwapOps = false; break;
770 SubIdx = PPC::sub_lt; SwapOps = true; break;
774 SubIdx = PPC::sub_gt; SwapOps = false; break;
778 SubIdx = PPC::sub_gt; SwapOps = true; break;
782 SubIdx
[all...]
/external/llvm/utils/TableGen/
H A DCodeGenRegisters.h347 // registers have a SubIdx sub-register.
349 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const {
350 return SubClassWithSubReg.lookup(SubIdx);
353 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx, argument
355 SubClassWithSubReg[SubIdx] = SubRC;
359 // containing only SubIdx super-registers of this class.
360 void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
364 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, argument
366 SuperRegClasses[SubIdx].insert(SuperRC);
/external/swiftshader/third_party/LLVM/include/llvm/Target/
H A DTargetRegisterInfo.h324 const char *getSubRegIndexName(unsigned SubIdx) const {
325 assert(SubIdx && "This is not a subregister index");
326 return SubRegIndexNames[SubIdx-1];
381 /// Reg so its sub-register of index SubIdx is Reg.
382 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, argument
385 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
703 unsigned SubIdx; member in class:llvm::PrintReg
706 : TRI(tri), Reg(reg), SubIdx(subidx) {}

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