/art/runtime/arch/x86_64/ |
H A D | thread_x86_64.cc | 33 static void arch_prctl(int code, void* val) { argument 34 syscall(__NR_arch_prctl, code, val);
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/art/compiler/dex/ |
H A D | verified_method.cc | 57 * Walks over the method code and adds any cast instructions in which 58 * the type cast is implicit to a set, which is used in the code generation 70 Instruction::Code code = inst->Opcode(); local 71 if (code == Instruction::CHECK_CAST) {
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/art/compiler/linker/x86/ |
H A D | relative_patcher_x86.cc | 24 void X86RelativePatcher::PatchPcRelativeReference(std::vector<uint8_t>* code, argument 33 DCHECK_LT(anchor_literal_offset, code->size()); 34 DCHECK_EQ((*code)[anchor_literal_offset - 5u], 0xe8u); 35 DCHECK_EQ((*code)[anchor_literal_offset - 4u], 0x00u); 36 DCHECK_EQ((*code)[anchor_literal_offset - 3u], 0x00u); 37 DCHECK_EQ((*code)[anchor_literal_offset - 2u], 0x00u); 38 DCHECK_EQ((*code)[anchor_literal_offset - 1u], 0x00u); 39 DCHECK_EQ((*code)[anchor_literal_offset] & 0xf8u, 0x58u); 44 DCHECK_LE(literal_offset, code->size()); 45 DCHECK_EQ((*code)[literal_offse [all...] |
H A D | relative_patcher_x86_base.cc | 37 void X86BaseRelativePatcher::PatchCall(std::vector<uint8_t>* code, argument 41 DCHECK_LE(literal_offset + 4u, code->size()); 47 reinterpret_cast<unaligned_int32_t*>(&(*code)[literal_offset])[0] = displacement;
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/art/compiler/linker/x86_64/ |
H A D | relative_patcher_x86_64.cc | 24 void X86_64RelativePatcher::PatchPcRelativeReference(std::vector<uint8_t>* code, argument 28 DCHECK_LE(patch.LiteralOffset() + 4u, code->size()); 34 reinterpret_cast<unaligned_int32_t*>(&(*code)[patch.LiteralOffset()])[0] = displacement; 37 void X86_64RelativePatcher::PatchBakerReadBarrierBranch(std::vector<uint8_t>* code ATTRIBUTE_UNUSED,
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/art/runtime/ |
H A D | dex_instruction_visitor.h | 28 void Visit(const uint16_t* code, size_t size_in_bytes) { argument 33 const Instruction* inst = Instruction::At(&code[i]);
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H A D | oat_file-inl.h | 26 const void* code = EntryPointToCodePointer(GetOatPointer<const void*>(code_offset_)); local 27 if (code == nullptr) { 30 // Return a pointer to the packed struct before the code. 31 return reinterpret_cast<const OatQuickMethodHeader*>(code) - 1; 51 const void* code = EntryPointToCodePointer(GetQuickCode()); local 52 if (code == nullptr) { 55 return reinterpret_cast<const OatQuickMethodHeader*>(code)[-1].GetFrameInfo().FrameSizeInBytes(); 59 const void* code = EntryPointToCodePointer(GetQuickCode()); local 60 if (code == nullptr) { 63 return reinterpret_cast<const OatQuickMethodHeader*>(code)[ 67 const void* code = EntryPointToCodePointer(GetQuickCode()); local 88 const void* code = EntryPointToCodePointer(GetOatPointer<const void*>(code_offset_)); local 100 const void* code = EntryPointToCodePointer(GetOatPointer<const void*>(code_offset_)); local [all...] |
H A D | dex_instruction_utils.h | 92 constexpr bool IsInstructionIGet(Instruction::Code code) { argument 93 return Instruction::IGET <= code && code <= Instruction::IGET_SHORT; 96 constexpr bool IsInstructionIPut(Instruction::Code code) { argument 97 return Instruction::IPUT <= code && code <= Instruction::IPUT_SHORT; 100 constexpr bool IsInstructionSGet(Instruction::Code code) { argument 101 return Instruction::SGET <= code && code <= Instruction::SGET_SHORT; 104 constexpr bool IsInstructionSPut(Instruction::Code code) { argument 108 IsInstructionAGet(Instruction::Code code) argument 112 IsInstructionAPut(Instruction::Code code) argument 116 IsInstructionIGetOrIPut(Instruction::Code code) argument 120 IsInstructionIGetQuickOrIPutQuick(Instruction::Code code) argument 125 IsInstructionSGetOrSPut(Instruction::Code code) argument 129 IsInstructionAGetOrAPut(Instruction::Code code) argument 133 IsInstructionBinOp2Addr(Instruction::Code code) argument 149 IGetMemAccessType(Instruction::Code code) argument 154 IPutMemAccessType(Instruction::Code code) argument 159 SGetMemAccessType(Instruction::Code code) argument 164 SPutMemAccessType(Instruction::Code code) argument 169 AGetMemAccessType(Instruction::Code code) argument 174 APutMemAccessType(Instruction::Code code) argument 179 IGetOrIPutMemAccessType(Instruction::Code code) argument 184 IGetQuickOrIPutQuickMemAccessType(Instruction::Code code) argument 207 SGetOrSPutMemAccessType(Instruction::Code code) argument 212 AGetOrAPutMemAccessType(Instruction::Code code) argument [all...] |
H A D | dex_instruction.cc | 542 std::ostream& operator<<(std::ostream& os, const Instruction::Code& code) { argument 543 return os << Instruction::Name(code);
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H A D | oat_quick_method_header.h | 31 // OatQuickMethodHeader precedes the raw code chunk generated by the compiler. 45 uintptr_t code = reinterpret_cast<uintptr_t>(code_ptr); local 46 uintptr_t header = code - OFFSETOF_MEMBER(OatQuickMethodHeader, code_); 47 DCHECK(IsAlignedParam(code, GetInstructionSetAlignment(kRuntimeISA)) || 49 << std::hex << code << " " << std::hex << header; 148 // (not `kThumb2`), *but* we always generate code for the Thumb-2 199 // The code size in bytes. The highest bit is used to signify if the compiled 200 // code with the method header has should_deoptimize flag. 202 // The actual code.
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H A D | utils.h | 214 uintptr_t code = reinterpret_cast<uintptr_t>(entry_point); local 215 // TODO: Make this Thumb2 specific. It is benign on other architectures as code is always at 217 code &= ~0x1; 218 return reinterpret_cast<const void*>(code);
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/art/compiler/linker/mips/ |
H A D | relative_patcher_mips.cc | 39 void MipsRelativePatcher::PatchCall(std::vector<uint8_t>* code ATTRIBUTE_UNUSED, 46 void MipsRelativePatcher::PatchPcRelativeReference(std::vector<uint8_t>* code, argument 59 DCHECK_GE(code->size(), 8u); 60 DCHECK_LE(literal_offset, code->size() - 8u); 63 DCHECK_EQ((*code)[literal_offset + 0], 0x34); 64 DCHECK_EQ((*code)[literal_offset + 1], 0x12); 65 DCHECK_EQ(((*code)[literal_offset + 2] & 0x1F), 0x1E); 66 DCHECK_EQ(((*code)[literal_offset + 3] & 0xFC), 0xEC); 68 DCHECK_EQ((*code)[literal_offset + 4], 0x78); 69 DCHECK_EQ((*code)[literal_offse [all...] |
/art/compiler/linker/mips64/ |
H A D | relative_patcher_mips64.cc | 39 void Mips64RelativePatcher::PatchCall(std::vector<uint8_t>* code, argument 44 DCHECK_GE(code->size(), 8u); 45 DCHECK_LE(literal_offset, code->size() - 8u); 47 DCHECK_EQ((*code)[literal_offset + 0], 0x34); 48 DCHECK_EQ((*code)[literal_offset + 1], 0x12); 49 DCHECK_EQ(((*code)[literal_offset + 2] & 0x1F), 0x1E); 50 DCHECK_EQ(((*code)[literal_offset + 3] & 0xFC), 0xEC); 52 DCHECK_EQ((*code)[literal_offset + 4], 0x78); 53 DCHECK_EQ((*code)[literal_offset + 5], 0x56); 54 DCHECK_EQ(((*code)[literal_offse 73 PatchPcRelativeReference(std::vector<uint8_t>* code, const LinkerPatch& patch, uint32_t patch_offset, uint32_t target_offset) argument [all...] |
/art/compiler/driver/ |
H A D | compiled_method_storage_test.cc | 50 ArrayRef<const uint8_t> code[] = { local 87 for (auto&& c : code) {
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H A D | compiled_method_storage.cc | 174 dedupe_code_("dedupe code", LengthPrefixedArrayAlloc<uint8_t>(swap_space_.get())), 202 const ArrayRef<const uint8_t>& code) { 203 return AllocateOrDeduplicateArray(code, &dedupe_code_); 206 void CompiledMethodStorage::ReleaseCode(const LengthPrefixedArray<uint8_t>* code) { argument 207 ReleaseArrayIfNotDeduplicated(code); 201 DeduplicateCode( const ArrayRef<const uint8_t>& code) argument
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H A D | compiler_driver_test.cc | 223 const void* code = m.GetEntryPointFromQuickCompiledCodePtrSize(pointer_size); local 224 ASSERT_NE(code, nullptr); 227 EXPECT_FALSE(class_linker->IsQuickToInterpreterBridge(code)); 229 EXPECT_TRUE(class_linker->IsQuickToInterpreterBridge(code)); 284 const void* code = m.GetEntryPointFromQuickCompiledCodePtrSize(pointer_size); local 285 ASSERT_NE(code, nullptr); 288 EXPECT_FALSE(class_linker->IsQuickToInterpreterBridge(code)); 290 EXPECT_TRUE(class_linker->IsQuickToInterpreterBridge(code));
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/art/compiler/linker/ |
H A D | multi_oat_relative_patcher.h | 34 // any number of oat files. It provides storage for method code offsets 50 // It must must never point directly to a method's code to avoid relative offsets 96 void PatchCall(std::vector<uint8_t>* code, argument 102 relative_patcher_->PatchCall(code, literal_offset, patch_offset, target_offset); 106 void PatchPcRelativeReference(std::vector<uint8_t>* code, argument 112 relative_patcher_->PatchPcRelativeReference(code, patch, patch_offset, target_offset); 115 void PatchBakerReadBarrierBranch(std::vector<uint8_t>* code, argument 119 relative_patcher_->PatchBakerReadBarrierBranch(code, patch, patch_offset);
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H A D | relative_patcher_test.h | 81 const ArrayRef<const uint8_t>& code, 87 code, 98 // We want to align the code rather than the preheader. 118 const auto code = compiled_method->GetQuickCode(); local 119 offset += code.size(); 149 ArrayRef<const uint8_t> code = compiled_method->GetQuickCode(); local 151 patched_code_.assign(code.begin(), code.end()); 152 code = ArrayRef<const uint8_t>(patched_code_); 183 out_.WriteFully(&code[ 79 AddCompiledMethod( MethodReference method_ref, const ArrayRef<const uint8_t>& code, const ArrayRef<const LinkerPatch>& patches = ArrayRef<const LinkerPatch>()) argument [all...] |
/art/compiler/utils/arm64/ |
H A D | assembler_arm64.h | 70 // Finalize the code. 73 // Size of generated code. 108 static vixl::aarch64::Register reg_x(int code) { argument 109 CHECK(code < kNumberOfXRegisters) << code; 110 if (code == SP) { 112 } else if (code == XZR) { 115 return vixl::aarch64::Register::GetXRegFromCode(code); 118 static vixl::aarch64::Register reg_w(int code) { 119 CHECK(code < kNumberOfWRegister [all...] |
/art/compiler/utils/mips/ |
H A D | assembler_mips32r6_test.cc | 62 // We put the code at address 0x1000000 (instead of 0) to avoid overlapping with the 69 // The GNU linker unconditionally pads the code segment with NOPs to a size that is a multiple 308 const char* code = ".set imm, {imm}\nlw ${reg}, ((imm - ((imm & 0x40000) << 1)) << 2)($pc)"; local 309 DriverStr(RepeatRIb(&mips::MipsAssembler::Lwpc, 19, code), "Lwpc"); 314 const char* code = ".set imm, {imm}\naddiupc ${reg}, (imm - ((imm & 0x40000) << 1)) << 2"; local 315 DriverStr(RepeatRIb(&mips::MipsAssembler::Addiupc, 19, code), "Addiupc");
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/art/compiler/ |
H A D | common_compiler_test.cc | 55 // If the code size is 0 it means the method was skipped due to profile guided compilation. 57 ArrayRef<const uint8_t> code = compiled_method->GetQuickCode(); local 58 const uint32_t code_size = code.size(); 83 chunk->insert(chunk->end(), code.begin(), code.end()); 93 MakeExecutable(code_ptr, code.size()); 96 LOG(INFO) << "MakeExecutable " << method->PrettyMethod() << " code=" << method_code; 99 // No code? You must mean to go into the interpreter.
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/art/compiler/jit/ |
H A D | jit_logger.cc | 102 // | jitted code binary | . 132 // A jitted code load event. 133 // In ART JIT, it is used to log a new method is jit compiled and committed to jit-code-cache. 134 // Note that such kLoad event supports code cache GC in ART JIT. 136 // each event/sample has time stamp. In case code cache GC happens in ART JIT, and a new 140 // JitCodeCache doesn't have to record any event on 'code delete'. 143 // A jitted code move event, i,e. a jitted code moved from one address to another address. 144 // It helps profiler to map samples to the right symbol even when the code is moved. 147 // it is moved to another address in jit-code 275 const void* code = osr ? code_cache->LookupOsrMethodHeader(method)->GetCode() local [all...] |
/art/compiler/linker/arm/ |
H A D | relative_patcher_thumb2.cc | 39 void Thumb2RelativePatcher::PatchCall(std::vector<uint8_t>* code, argument 43 DCHECK_LE(literal_offset + 4u, code->size()); 62 DCHECK_EQ(GetInsn32(code, literal_offset) & 0xf800d000, 0xf000d000); 64 SetInsn32(code, literal_offset, value); 67 void Thumb2RelativePatcher::PatchPcRelativeReference(std::vector<uint8_t>* code, argument 76 uint32_t insn = GetInsn32(code, literal_offset); 84 SetInsn32(code, literal_offset, insn); 87 void Thumb2RelativePatcher::PatchBakerReadBarrierBranch(std::vector<uint8_t>* code ATTRIBUTE_UNUSED, 112 MemoryRegion code(thunk_code.data(), thunk_code.size()); 113 assembler.FinalizeInstructions(code); 127 SetInsn32(std::vector<uint8_t>* code, uint32_t offset, uint32_t value) argument 137 GetInsn32(ArrayRef<const uint8_t> code, uint32_t offset) argument 149 GetInsn32(Vector* code, uint32_t offset) argument [all...] |
/art/compiler/optimizing/ |
H A D | common_arm64.h | 46 inline int VIXLRegCodeFromART(int code) { argument 47 if (code == SP) { 50 if (code == XZR) { 53 return code; 56 inline int ARTRegCodeFromVIXL(int code) { argument 57 if (code == vixl::aarch64::kSPRegInternalCode) { 60 if (code == vixl::aarch64::kZeroRegCode) { 63 return code; 247 // Our code generator ensures shift distances are within an encodable range. 286 // Check if registers in art register set have the same register code i [all...] |
/art/compiler/utils/ |
H A D | assembler_thumb_test.cc | 95 void DumpAndCheck(std::vector<uint8_t>& code, const char* testname, const char* const* results) { argument 115 for (uint32_t i = 0 ; i < code.size(); ++i) { 116 out << ".byte " << (static_cast<int>(code[i]) & 0xff) << "\n"; 142 // into the .inc file, so let's add the appropriate prefix/suffix needed in the C++ code. 186 MemoryRegion code(&managed_code[0], managed_code.size()); 187 __ FinalizeInstructions(code); 287 __ rsbs(R0, R0, ShifterOperand(0)); // Check Rd == Rn code path. 1628 MemoryRegion code(&managed_code[0], managed_code.size()); 1629 __ FinalizeInstructions(code);
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