Searched defs:instruction (Results 1 - 25 of 82) sorted by relevance

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/art/compiler/optimizing/
H A Dinstruction_simplifier_arm.h38 bool TryMergeIntoUsersShifterOperand(HInstruction* instruction);
57 HInstruction* instruction = it.Current(); variable
58 if (instruction->IsInBlock()) {
59 instruction->Accept(this);
64 void VisitAnd(HAnd* instruction) OVERRIDE;
65 void VisitArrayGet(HArrayGet* instruction) OVERRIDE;
66 void VisitArraySet(HArraySet* instruction) OVERRIDE;
67 void VisitMul(HMul* instruction) OVERRIDE;
68 void VisitOr(HOr* instruction) OVERRIDE;
69 void VisitShl(HShl* instruction) OVERRID
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H A Dinstruction_simplifier_arm64.h38 bool TryMergeIntoUsersShifterOperand(HInstruction* instruction);
59 HInstruction* instruction = it.Current(); variable
60 if (instruction->IsInBlock()) {
61 instruction->Accept(this);
67 void VisitAnd(HAnd* instruction) OVERRIDE;
68 void VisitArrayGet(HArrayGet* instruction) OVERRIDE;
69 void VisitArraySet(HArraySet* instruction) OVERRIDE;
70 void VisitMul(HMul* instruction) OVERRIDE;
71 void VisitOr(HOr* instruction) OVERRIDE;
72 void VisitShl(HShl* instruction) OVERRID
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H A Dinstruction_simplifier_shared.h26 inline bool CanFitInShifterOperand(HInstruction* instruction) { argument
27 if (instruction->IsTypeConversion()) {
28 HTypeConversion* conversion = instruction->AsTypeConversion();
35 return (instruction->IsShl() && instruction->AsShl()->InputAt(1)->IsIntConstant()) ||
36 (instruction->IsShr() && instruction->AsShr()->InputAt(1)->IsIntConstant()) ||
37 (instruction->IsUShr() && instruction->AsUShr()->InputAt(1)->IsIntConstant());
53 // a negated bitwise instruction
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H A Dnodes_shared.cc24 void HDataProcWithShifterOp::GetOpInfoFromInstruction(HInstruction* instruction, argument
27 DCHECK(CanFitInShifterOperand(instruction));
28 if (instruction->IsShl()) {
30 *shift_amount = instruction->AsShl()->GetRight()->AsIntConstant()->GetValue();
31 } else if (instruction->IsShr()) {
33 *shift_amount = instruction->AsShr()->GetRight()->AsIntConstant()->GetValue();
34 } else if (instruction->IsUShr()) {
36 *shift_amount = instruction->AsUShr()->GetRight()->AsIntConstant()->GetValue();
38 DCHECK(instruction->IsTypeConversion());
39 Primitive::Type result_type = instruction
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H A Dside_effects_analysis.cc45 HInstruction* instruction = inst_it.Current(); local
46 effects = effects.Union(instruction->GetSideEffects());
H A Dlicm.cc23 static bool IsPhiOf(HInstruction* instruction, HBasicBlock* block) { argument
24 return instruction->IsPhi() && instruction->GetBlock() == block;
28 * Returns whether `instruction` has all its inputs and environment defined
31 static bool InputsAreDefinedBeforeLoop(HInstruction* instruction) { argument
32 DCHECK(instruction->IsInLoop());
33 HLoopInformation* info = instruction->GetBlock()->GetLoopInformation();
34 for (const HInstruction* input : instruction->GetInputs()) {
43 for (HEnvironment* environment = instruction->GetEnvironment();
51 // We can move an instruction tha
131 HInstruction* instruction = inst_it.Current(); local
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H A Dlocations.cc29 LocationSummary::LocationSummary(HInstruction* instruction, argument
32 : inputs_(instruction->InputCount(),
33 instruction->GetBlock()->GetGraph()->GetArena()->Adapter(kArenaAllocLocationSummary)),
34 temps_(instruction->GetBlock()->GetGraph()->GetArena()->Adapter(kArenaAllocLocationSummary)),
43 instruction->SetLocations(this);
46 ArenaAllocator* arena = instruction->GetBlock()->GetGraph()->GetArena();
52 Location Location::RegisterOrConstant(HInstruction* instruction) { argument
53 return instruction->IsConstant()
54 ? Location::ConstantLocation(instruction->AsConstant())
58 Location Location::RegisterOrInt32Constant(HInstruction* instruction) { argument
69 FpuRegisterOrInt32Constant(HInstruction* instruction) argument
80 ByteRegisterOrConstant(int reg, HInstruction* instruction) argument
86 FpuRegisterOrConstant(HInstruction* instruction) argument
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H A Dpretty_printer.h30 void PrintPreInstruction(HInstruction* instruction) { argument
32 PrintInt(instruction->GetId());
36 void VisitInstruction(HInstruction* instruction) OVERRIDE {
37 PrintPreInstruction(instruction); variable
38 PrintString(instruction->DebugName());
39 PrintPostInstruction(instruction); variable
42 void PrintPostInstruction(HInstruction* instruction) { argument
43 HConstInputsRef inputs = instruction->GetInputs();
57 if (instruction->HasUses()) {
60 for (const HUseListNode<HInstruction*>& use : instruction
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H A Dcha_guard_optimization.cc31 // (such as GVN or instruction simplifier).
66 // advance the iterator due to removing/moving more than one instruction.
95 // Advance instruction iterator first before we remove the guard.
149 HInstruction* instruction; local
153 instruction = flag->GetPrevious();
155 // Search backward from the last instruction of that dominator.
156 instruction = dominator->GetLastInstruction();
158 while (instruction != receiver) {
159 if (instruction == nullptr) {
161 // in the instruction lis
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H A Dinduction_var_range.h27 * a conservative lower and upper bound value or last value on each instruction in the HIR.
40 * A value that can be represented as "a * instruction + b" for 32-bit constants, where
46 Value() : instruction(nullptr), a_constant(0), b_constant(0), is_known(false) {}
48 : instruction(a != 0 ? i : nullptr), a_constant(a), b_constant(b), is_known(true) {}
50 // Representation as: a_constant x instruction + b_constant.
51 HInstruction* instruction; member in struct:art::InductionVarRange::Value
61 * Given a context denoted by the first instruction, returns a possibly conservative lower
62 * and upper bound on the instruction's value in the output parameters min_val and max_val,
65 * instruction at which chasing may stop. Returns false on failure.
68 HInstruction* instruction,
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H A Dselect_generator.cc24 // contains at most `kMaxInstructionsInBranch` other movable instruction with
34 HInstruction* instruction = it.Current(); local
35 if (instruction->IsControlFlow()) {
36 return instruction->IsGoto() && num_instructions <= kMaxInstructionsInBranch;
37 } else if (instruction->CanBeMoved() && !instruction->HasSideEffects()) {
95 // TODO(dbrazdil): This puts an instruction between If and its condition.
118 // Create the Select instruction and insert it in front of the If.
H A Dcode_generator_vector_arm.cc25 void LocationsBuilderARM::VisitVecReplicateScalar(HVecReplicateScalar* instruction) { argument
26 LOG(FATAL) << "No SIMD for " << instruction->GetId();
29 void InstructionCodeGeneratorARM::VisitVecReplicateScalar(HVecReplicateScalar* instruction) { argument
30 LOG(FATAL) << "No SIMD for " << instruction->GetId();
33 void LocationsBuilderARM::VisitVecSetScalars(HVecSetScalars* instruction) { argument
34 LOG(FATAL) << "No SIMD for " << instruction->GetId();
37 void InstructionCodeGeneratorARM::VisitVecSetScalars(HVecSetScalars* instruction) { argument
38 LOG(FATAL) << "No SIMD for " << instruction->GetId();
41 void LocationsBuilderARM::VisitVecSumReduce(HVecSumReduce* instruction) { argument
42 LOG(FATAL) << "No SIMD for " << instruction
45 VisitVecSumReduce(HVecSumReduce* instruction) argument
50 CreateVecUnOpLocations(ArenaAllocator* arena, HVecUnaryOperation* instruction) argument
68 VisitVecCnv(HVecCnv* instruction) argument
72 VisitVecCnv(HVecCnv* instruction) argument
76 VisitVecNeg(HVecNeg* instruction) argument
80 VisitVecNeg(HVecNeg* instruction) argument
84 VisitVecAbs(HVecAbs* instruction) argument
88 VisitVecAbs(HVecAbs* instruction) argument
92 VisitVecNot(HVecNot* instruction) argument
96 VisitVecNot(HVecNot* instruction) argument
101 CreateVecBinOpLocations(ArenaAllocator* arena, HVecBinaryOperation* instruction) argument
119 VisitVecAdd(HVecAdd* instruction) argument
123 VisitVecAdd(HVecAdd* instruction) argument
127 VisitVecHalvingAdd(HVecHalvingAdd* instruction) argument
131 VisitVecHalvingAdd(HVecHalvingAdd* instruction) argument
135 VisitVecSub(HVecSub* instruction) argument
139 VisitVecSub(HVecSub* instruction) argument
143 VisitVecMul(HVecMul* instruction) argument
147 VisitVecMul(HVecMul* instruction) argument
151 VisitVecDiv(HVecDiv* instruction) argument
155 VisitVecDiv(HVecDiv* instruction) argument
159 VisitVecMin(HVecMin* instruction) argument
163 VisitVecMin(HVecMin* instruction) argument
167 VisitVecMax(HVecMax* instruction) argument
171 VisitVecMax(HVecMax* instruction) argument
175 VisitVecAnd(HVecAnd* instruction) argument
179 VisitVecAnd(HVecAnd* instruction) argument
183 VisitVecAndNot(HVecAndNot* instruction) argument
187 VisitVecAndNot(HVecAndNot* instruction) argument
191 VisitVecOr(HVecOr* instruction) argument
195 VisitVecOr(HVecOr* instruction) argument
199 VisitVecXor(HVecXor* instruction) argument
203 VisitVecXor(HVecXor* instruction) argument
208 CreateVecShiftLocations(ArenaAllocator* arena, HVecBinaryOperation* instruction) argument
224 VisitVecShl(HVecShl* instruction) argument
228 VisitVecShl(HVecShl* instruction) argument
232 VisitVecShr(HVecShr* instruction) argument
236 VisitVecShr(HVecShr* instruction) argument
240 VisitVecUShr(HVecUShr* instruction) argument
244 VisitVecUShr(HVecUShr* instruction) argument
256 VisitVecLoad(HVecLoad* instruction) argument
260 VisitVecLoad(HVecLoad* instruction) argument
264 VisitVecStore(HVecStore* instruction) argument
268 VisitVecStore(HVecStore* instruction) argument
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H A Dcode_generator_vector_arm_vixl.cc25 void LocationsBuilderARMVIXL::VisitVecReplicateScalar(HVecReplicateScalar* instruction) { argument
26 LOG(FATAL) << "No SIMD for " << instruction->GetId();
29 void InstructionCodeGeneratorARMVIXL::VisitVecReplicateScalar(HVecReplicateScalar* instruction) { argument
30 LOG(FATAL) << "No SIMD for " << instruction->GetId();
33 void LocationsBuilderARMVIXL::VisitVecSetScalars(HVecSetScalars* instruction) { argument
34 LOG(FATAL) << "No SIMD for " << instruction->GetId();
37 void InstructionCodeGeneratorARMVIXL::VisitVecSetScalars(HVecSetScalars* instruction) { argument
38 LOG(FATAL) << "No SIMD for " << instruction->GetId();
41 void LocationsBuilderARMVIXL::VisitVecSumReduce(HVecSumReduce* instruction) { argument
42 LOG(FATAL) << "No SIMD for " << instruction
45 VisitVecSumReduce(HVecSumReduce* instruction) argument
50 CreateVecUnOpLocations(ArenaAllocator* arena, HVecUnaryOperation* instruction) argument
68 VisitVecCnv(HVecCnv* instruction) argument
72 VisitVecCnv(HVecCnv* instruction) argument
76 VisitVecNeg(HVecNeg* instruction) argument
80 VisitVecNeg(HVecNeg* instruction) argument
84 VisitVecAbs(HVecAbs* instruction) argument
88 VisitVecAbs(HVecAbs* instruction) argument
92 VisitVecNot(HVecNot* instruction) argument
96 VisitVecNot(HVecNot* instruction) argument
101 CreateVecBinOpLocations(ArenaAllocator* arena, HVecBinaryOperation* instruction) argument
119 VisitVecAdd(HVecAdd* instruction) argument
123 VisitVecAdd(HVecAdd* instruction) argument
127 VisitVecHalvingAdd(HVecHalvingAdd* instruction) argument
131 VisitVecHalvingAdd(HVecHalvingAdd* instruction) argument
135 VisitVecSub(HVecSub* instruction) argument
139 VisitVecSub(HVecSub* instruction) argument
143 VisitVecMul(HVecMul* instruction) argument
147 VisitVecMul(HVecMul* instruction) argument
151 VisitVecDiv(HVecDiv* instruction) argument
155 VisitVecDiv(HVecDiv* instruction) argument
159 VisitVecMin(HVecMin* instruction) argument
163 VisitVecMin(HVecMin* instruction) argument
167 VisitVecMax(HVecMax* instruction) argument
171 VisitVecMax(HVecMax* instruction) argument
175 VisitVecAnd(HVecAnd* instruction) argument
179 VisitVecAnd(HVecAnd* instruction) argument
183 VisitVecAndNot(HVecAndNot* instruction) argument
187 VisitVecAndNot(HVecAndNot* instruction) argument
191 VisitVecOr(HVecOr* instruction) argument
195 VisitVecOr(HVecOr* instruction) argument
199 VisitVecXor(HVecXor* instruction) argument
203 VisitVecXor(HVecXor* instruction) argument
208 CreateVecShiftLocations(ArenaAllocator* arena, HVecBinaryOperation* instruction) argument
224 VisitVecShl(HVecShl* instruction) argument
228 VisitVecShl(HVecShl* instruction) argument
232 VisitVecShr(HVecShr* instruction) argument
236 VisitVecShr(HVecShr* instruction) argument
240 VisitVecUShr(HVecUShr* instruction) argument
244 VisitVecUShr(HVecUShr* instruction) argument
256 VisitVecLoad(HVecLoad* instruction) argument
260 VisitVecLoad(HVecLoad* instruction) argument
264 VisitVecStore(HVecStore* instruction) argument
268 VisitVecStore(HVecStore* instruction) argument
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H A Dcode_generator_vector_mips.cc25 void LocationsBuilderMIPS::VisitVecReplicateScalar(HVecReplicateScalar* instruction) { argument
26 LOG(FATAL) << "No SIMD for " << instruction->GetId();
29 void InstructionCodeGeneratorMIPS::VisitVecReplicateScalar(HVecReplicateScalar* instruction) { argument
30 LOG(FATAL) << "No SIMD for " << instruction->GetId();
33 void LocationsBuilderMIPS::VisitVecSetScalars(HVecSetScalars* instruction) { argument
34 LOG(FATAL) << "No SIMD for " << instruction->GetId();
37 void InstructionCodeGeneratorMIPS::VisitVecSetScalars(HVecSetScalars* instruction) { argument
38 LOG(FATAL) << "No SIMD for " << instruction->GetId();
41 void LocationsBuilderMIPS::VisitVecSumReduce(HVecSumReduce* instruction) { argument
42 LOG(FATAL) << "No SIMD for " << instruction
45 VisitVecSumReduce(HVecSumReduce* instruction) argument
50 CreateVecUnOpLocations(ArenaAllocator* arena, HVecUnaryOperation* instruction) argument
68 VisitVecCnv(HVecCnv* instruction) argument
72 VisitVecCnv(HVecCnv* instruction) argument
76 VisitVecNeg(HVecNeg* instruction) argument
80 VisitVecNeg(HVecNeg* instruction) argument
84 VisitVecAbs(HVecAbs* instruction) argument
88 VisitVecAbs(HVecAbs* instruction) argument
92 VisitVecNot(HVecNot* instruction) argument
96 VisitVecNot(HVecNot* instruction) argument
101 CreateVecBinOpLocations(ArenaAllocator* arena, HVecBinaryOperation* instruction) argument
119 VisitVecAdd(HVecAdd* instruction) argument
123 VisitVecAdd(HVecAdd* instruction) argument
127 VisitVecHalvingAdd(HVecHalvingAdd* instruction) argument
131 VisitVecHalvingAdd(HVecHalvingAdd* instruction) argument
135 VisitVecSub(HVecSub* instruction) argument
139 VisitVecSub(HVecSub* instruction) argument
143 VisitVecMul(HVecMul* instruction) argument
147 VisitVecMul(HVecMul* instruction) argument
151 VisitVecDiv(HVecDiv* instruction) argument
155 VisitVecDiv(HVecDiv* instruction) argument
159 VisitVecMin(HVecMin* instruction) argument
163 VisitVecMin(HVecMin* instruction) argument
167 VisitVecMax(HVecMax* instruction) argument
171 VisitVecMax(HVecMax* instruction) argument
175 VisitVecAnd(HVecAnd* instruction) argument
179 VisitVecAnd(HVecAnd* instruction) argument
183 VisitVecAndNot(HVecAndNot* instruction) argument
187 VisitVecAndNot(HVecAndNot* instruction) argument
191 VisitVecOr(HVecOr* instruction) argument
195 VisitVecOr(HVecOr* instruction) argument
199 VisitVecXor(HVecXor* instruction) argument
203 VisitVecXor(HVecXor* instruction) argument
208 CreateVecShiftLocations(ArenaAllocator* arena, HVecBinaryOperation* instruction) argument
224 VisitVecShl(HVecShl* instruction) argument
228 VisitVecShl(HVecShl* instruction) argument
232 VisitVecShr(HVecShr* instruction) argument
236 VisitVecShr(HVecShr* instruction) argument
240 VisitVecUShr(HVecUShr* instruction) argument
244 VisitVecUShr(HVecUShr* instruction) argument
256 VisitVecLoad(HVecLoad* instruction) argument
260 VisitVecLoad(HVecLoad* instruction) argument
264 VisitVecStore(HVecStore* instruction) argument
268 VisitVecStore(HVecStore* instruction) argument
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H A Dcode_generator_vector_mips64.cc25 void LocationsBuilderMIPS64::VisitVecReplicateScalar(HVecReplicateScalar* instruction) { argument
26 LOG(FATAL) << "No SIMD for " << instruction->GetId();
29 void InstructionCodeGeneratorMIPS64::VisitVecReplicateScalar(HVecReplicateScalar* instruction) { argument
30 LOG(FATAL) << "No SIMD for " << instruction->GetId();
33 void LocationsBuilderMIPS64::VisitVecSetScalars(HVecSetScalars* instruction) { argument
34 LOG(FATAL) << "No SIMD for " << instruction->GetId();
37 void InstructionCodeGeneratorMIPS64::VisitVecSetScalars(HVecSetScalars* instruction) { argument
38 LOG(FATAL) << "No SIMD for " << instruction->GetId();
41 void LocationsBuilderMIPS64::VisitVecSumReduce(HVecSumReduce* instruction) { argument
42 LOG(FATAL) << "No SIMD for " << instruction
45 VisitVecSumReduce(HVecSumReduce* instruction) argument
50 CreateVecUnOpLocations(ArenaAllocator* arena, HVecUnaryOperation* instruction) argument
68 VisitVecCnv(HVecCnv* instruction) argument
72 VisitVecCnv(HVecCnv* instruction) argument
76 VisitVecNeg(HVecNeg* instruction) argument
80 VisitVecNeg(HVecNeg* instruction) argument
84 VisitVecAbs(HVecAbs* instruction) argument
88 VisitVecAbs(HVecAbs* instruction) argument
92 VisitVecNot(HVecNot* instruction) argument
96 VisitVecNot(HVecNot* instruction) argument
101 CreateVecBinOpLocations(ArenaAllocator* arena, HVecBinaryOperation* instruction) argument
119 VisitVecAdd(HVecAdd* instruction) argument
123 VisitVecAdd(HVecAdd* instruction) argument
127 VisitVecHalvingAdd(HVecHalvingAdd* instruction) argument
131 VisitVecHalvingAdd(HVecHalvingAdd* instruction) argument
135 VisitVecSub(HVecSub* instruction) argument
139 VisitVecSub(HVecSub* instruction) argument
143 VisitVecMul(HVecMul* instruction) argument
147 VisitVecMul(HVecMul* instruction) argument
151 VisitVecDiv(HVecDiv* instruction) argument
155 VisitVecDiv(HVecDiv* instruction) argument
159 VisitVecMin(HVecMin* instruction) argument
163 VisitVecMin(HVecMin* instruction) argument
167 VisitVecMax(HVecMax* instruction) argument
171 VisitVecMax(HVecMax* instruction) argument
175 VisitVecAnd(HVecAnd* instruction) argument
179 VisitVecAnd(HVecAnd* instruction) argument
183 VisitVecAndNot(HVecAndNot* instruction) argument
187 VisitVecAndNot(HVecAndNot* instruction) argument
191 VisitVecOr(HVecOr* instruction) argument
195 VisitVecOr(HVecOr* instruction) argument
199 VisitVecXor(HVecXor* instruction) argument
203 VisitVecXor(HVecXor* instruction) argument
208 CreateVecShiftLocations(ArenaAllocator* arena, HVecBinaryOperation* instruction) argument
224 VisitVecShl(HVecShl* instruction) argument
228 VisitVecShl(HVecShl* instruction) argument
232 VisitVecShr(HVecShr* instruction) argument
236 VisitVecShr(HVecShr* instruction) argument
240 VisitVecUShr(HVecUShr* instruction) argument
244 VisitVecUShr(HVecUShr* instruction) argument
256 VisitVecLoad(HVecLoad* instruction) argument
260 VisitVecLoad(HVecLoad* instruction) argument
264 VisitVecStore(HVecStore* instruction) argument
268 VisitVecStore(HVecStore* instruction) argument
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H A Dcode_sinking.cc39 static bool IsInterestingInstruction(HInstruction* instruction) { argument
41 if (instruction->GetBlock() == instruction->GetBlock()->GetGraph()->GetEntryBlock()) {
48 if (instruction->IsInstanceFieldSet()) {
49 if (instruction->AsInstanceFieldSet()->IsVolatile()) {
55 if (instruction->IsNewInstance() || instruction->IsNewArray()) {
60 if (instruction->CanThrow()) {
68 if (instruction->IsInstanceFieldSet()) {
69 if (!instruction
99 AddInstruction(HInstruction* instruction, const ArenaBitVector& processed_instructions, const ArenaBitVector& discard_blocks, ArenaVector<HInstruction*>* worklist) argument
112 AddInputs(HInstruction* instruction, const ArenaBitVector& processed_instructions, const ArenaBitVector& discard_blocks, ArenaVector<HInstruction*>* worklist) argument
133 ShouldFilterUse(HInstruction* instruction, HInstruction* user, const ArenaBitVector& post_dominated) argument
154 FindIdealPosition(HInstruction* instruction, const ArenaBitVector& post_dominated, bool filter = false) argument
285 HInstruction* instruction = worklist.back(); local
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H A Dconstant_folding.cc50 void VisitEqual(HEqual* instruction) OVERRIDE;
51 void VisitNotEqual(HNotEqual* instruction) OVERRIDE;
53 void VisitAbove(HAbove* instruction) OVERRIDE;
54 void VisitAboveOrEqual(HAboveOrEqual* instruction) OVERRIDE;
55 void VisitBelow(HBelow* instruction) OVERRIDE;
56 void VisitBelowOrEqual(HBelowOrEqual* instruction) OVERRIDE;
58 void VisitAnd(HAnd* instruction) OVERRIDE;
59 void VisitCompare(HCompare* instruction) OVERRIDE;
60 void VisitMul(HMul* instruction) OVERRIDE;
61 void VisitOr(HOr* instruction) OVERRID
133 VisitShift(HBinaryOperation* instruction) argument
146 VisitEqual(HEqual* instruction) argument
158 VisitNotEqual(HNotEqual* instruction) argument
170 VisitAbove(HAbove* instruction) argument
182 VisitAboveOrEqual(HAboveOrEqual* instruction) argument
194 VisitBelow(HBelow* instruction) argument
206 VisitBelowOrEqual(HBelowOrEqual* instruction) argument
218 VisitAnd(HAnd* instruction) argument
230 VisitCompare(HCompare* instruction) argument
250 VisitMul(HMul* instruction) argument
267 VisitOr(HOr* instruction) argument
284 VisitRem(HRem* instruction) argument
320 VisitShl(HShl* instruction) argument
324 VisitShr(HShr* instruction) argument
328 VisitSub(HSub* instruction) argument
353 VisitUShr(HUShr* instruction) argument
357 VisitXor(HXor* instruction) argument
[all...]
H A Dinstruction_simplifier_arm.cc106 // Merge a bitfield move instruction into its uses if it can be merged in all of them.
116 // Check whether we can merge the instruction in all its users' shifter operand.
127 // Merge the instruction into its uses.
139 void InstructionSimplifierArmVisitor::VisitAnd(HAnd* instruction) { argument
140 if (TryMergeNegatedInput(instruction)) {
145 void InstructionSimplifierArmVisitor::VisitArrayGet(HArrayGet* instruction) { argument
146 size_t data_offset = CodeGenerator::GetArrayDataOffset(instruction);
147 Primitive::Type type = instruction->GetType();
153 if (mirror::kUseStringCompression && instruction->IsStringCharAt()) {
165 if (TryExtractArrayAccessAddress(instruction,
173 VisitArraySet(HArraySet* instruction) argument
194 VisitMul(HMul* instruction) argument
200 VisitOr(HOr* instruction) argument
206 VisitShl(HShl* instruction) argument
212 VisitShr(HShr* instruction) argument
218 VisitTypeConversion(HTypeConversion* instruction) argument
232 VisitUShr(HUShr* instruction) argument
[all...]
H A Dinstruction_simplifier_arm64.cc103 // Merge a bitfield move instruction into its uses if it can be merged in all of them.
113 // Check whether we can merge the instruction in all its users' shifter operand.
124 // Merge the instruction into its uses.
136 void InstructionSimplifierArm64Visitor::VisitAnd(HAnd* instruction) { argument
137 if (TryMergeNegatedInput(instruction)) {
142 void InstructionSimplifierArm64Visitor::VisitArrayGet(HArrayGet* instruction) { argument
143 size_t data_offset = CodeGenerator::GetArrayDataOffset(instruction);
144 if (TryExtractArrayAccessAddress(instruction,
145 instruction->GetArray(),
146 instruction
152 VisitArraySet(HArraySet* instruction) argument
163 VisitMul(HMul* instruction) argument
169 VisitOr(HOr* instruction) argument
175 VisitShl(HShl* instruction) argument
181 VisitShr(HShr* instruction) argument
187 VisitTypeConversion(HTypeConversion* instruction) argument
201 VisitUShr(HUShr* instruction) argument
207 VisitXor(HXor* instruction) argument
213 VisitVecMul(HVecMul* instruction) argument
[all...]
H A Doptimizing_unit_test.h124 // Returns if the instruction is removed from the graph.
125 inline bool IsRemoved(HInstruction* instruction) { argument
126 return instruction->GetBlock() == nullptr;
H A Dprepare_for_register_allocation.cc45 // Replace the uses with the actual guarded instruction.
72 void PrepareForRegisterAllocation::VisitArraySet(HArraySet* instruction) { argument
73 HInstruction* value = instruction->GetValue();
79 if (instruction->NeedsTypeCheck()) {
80 instruction->ClearNeedsTypeCheck();
136 // Pass the initialization duty to the `HLoadClass` instruction,
137 // and remove the instruction from the graph.
177 // Keeping track of the initializing instruction is no longer required
188 // Determine if input and user come from the same dex instruction, so that we can move
198 // Now do a thorough environment check that this is really coming from the same instruction i
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H A Dscheduler_arm64.cc41 // Although the code generated is a simple `add` instruction, we found through empirical results
50 void SchedulingLatencyVisitorARM64::VisitArrayGet(HArrayGet* instruction) { argument
51 if (!instruction->GetArray()->IsIntermediateAddress()) {
136 void SchedulingLatencyVisitorARM64::VisitNewInstance(HNewInstance* instruction) { argument
137 if (instruction->IsStringAlloc()) {
145 void SchedulingLatencyVisitorARM64::VisitRem(HRem* instruction) { argument
146 if (Primitive::IsFloatingPointType(instruction->GetResultType())) {
151 if (instruction->GetRight()->IsConstant()) {
152 int64_t imm = Int64FromConstant(instruction->GetRight()->AsConstant());
178 void SchedulingLatencyVisitorARM64::VisitSuspendCheck(HSuspendCheck* instruction) { argument
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H A Dsharpening.cc42 HInstruction* instruction = it.Current(); local
43 if (instruction->IsInvokeStaticOrDirect()) {
44 SharpenInvokeStaticOrDirect(instruction->AsInvokeStaticOrDirect(), codegen_);
45 } else if (instruction->IsLoadString()) {
46 ProcessLoadString(instruction->AsLoadString());
/art/runtime/
H A Ddex_instruction_test.cc72 uint16_t instruction[4]; local
74 0xcafe /* arg_regs */, instruction);
76 const Instruction* ins = Instruction::At(instruction);
82 ASSERT_EQ(4u, ins->VRegA_45cc(instruction[0]));
107 uint16_t instruction[4]; local
109 0xcafe /* arg_regs */, instruction);
111 const Instruction* ins = Instruction::At(instruction);
117 ASSERT_EQ(4u, ins->VRegA_4rcc(instruction[0]));
/art/runtime/jit/
H A Dprofiling_info.cc53 const Instruction& instruction = *Instruction::At(code_ptr); local
54 switch (instruction.Opcode()) {
67 dex_pc += instruction.SizeInCodeUnits();
68 code_ptr += instruction.SizeInCodeUnits();
71 // We always create a `ProfilingInfo` object, even if there is no instruction we are

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