Searched defs:out_reg_lo (Results 1 - 4 of 4) sorted by relevance

/art/compiler/optimizing/
H A Dintrinsics_arm.cc427 Register out_reg_lo = output.AsRegisterPairLow<Register>(); local
430 DCHECK_NE(out_reg_lo, in_reg_hi) << "Diagonal overlap unexpected.";
433 __ adds(out_reg_lo, in_reg_lo, ShifterOperand(mask));
435 __ eor(out_reg_lo, mask, ShifterOperand(out_reg_lo));
2368 Register out_reg_lo = locations->Out().AsRegisterPairLow<Register>(); local
2371 __ rbit(out_reg_lo, in_reg_hi);
2403 Register out_reg_lo = locations->Out().AsRegisterPairLow<Register>(); local
2406 __ rev(out_reg_lo, in_reg_hi);
H A Dintrinsics_arm_vixl.cc485 vixl32::Register out_reg_lo = LowRegisterFrom(output); local
488 DCHECK(!out_reg_lo.Is(in_reg_hi)) << "Diagonal overlap unexpected.";
491 __ Adds(out_reg_lo, in_reg_lo, mask);
493 __ Eor(out_reg_lo, mask, out_reg_lo);
2741 vixl32::Register out_reg_lo = LowRegisterFrom(locations->Out()); local
2744 __ Rbit(out_reg_lo, in_reg_hi);
2771 vixl32::Register out_reg_lo = LowRegisterFrom(locations->Out()); local
2774 __ Rev(out_reg_lo, in_reg_hi);
H A Dcode_generator_arm.cc4488 Register out_reg_lo = locations->Out().AsRegisterPairLow<Register>(); local
4506 __ Lsr(out_reg_lo, in_reg_lo, rot);
4507 __ orr(out_reg_lo, out_reg_lo, ShifterOperand(in_reg_hi, arm::LSL, kArmBitsPerWord - rot));
4509 __ Mov(out_reg_lo, in_reg_lo);
4525 // out_reg_lo = (reg_lo << shift_left) | (reg_hi >> shift_right).
4527 __ Lsr(out_reg_lo, in_reg_lo, shift_right);
4528 __ add(out_reg_hi, out_reg_hi, ShifterOperand(out_reg_lo));
4529 __ Lsl(out_reg_lo, in_reg_lo, shift_left);
4531 __ add(out_reg_lo, out_reg_l
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H A Dcode_generator_arm_vixl.cc4471 vixl32::Register out_reg_lo = LowRegisterFrom(locations->Out()); local
4489 __ Lsr(out_reg_lo, in_reg_lo, Operand::From(rot));
4490 __ Orr(out_reg_lo, out_reg_lo, Operand(in_reg_hi, ShiftType::LSL, kArmBitsPerWord - rot));
4492 __ Mov(out_reg_lo, in_reg_lo);
4508 // out_reg_lo = (reg_lo << shift_left) | (reg_hi >> shift_right).
4510 __ Lsr(out_reg_lo, in_reg_lo, shift_right);
4511 __ Add(out_reg_hi, out_reg_hi, out_reg_lo);
4512 __ Lsl(out_reg_lo, in_reg_lo, shift_left);
4514 __ Add(out_reg_lo, out_reg_l
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