/external/vixl/src/ |
H A D | utils-vixl.cc | 131 unsigned CountClearHalfWords(uint64_t imm, unsigned reg_size) { argument 132 VIXL_ASSERT((reg_size % 8) == 0); 134 for (unsigned i = 0; i < (reg_size / 16); i++) {
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/external/v8/src/arm64/ |
H A D | instructions-arm64.cc | 75 static uint64_t RepeatBitsAcrossReg(unsigned reg_size, argument 80 DCHECK((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits)); 82 for (unsigned i = width; i < reg_size; i *= 2) { 93 unsigned reg_size = SixtyFourBits() ? kXRegSizeInBits : kWRegSizeInBits; local 132 return RepeatBitsAcrossReg(reg_size,
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H A D | assembler-arm64.h | 131 int reg_size; member in struct:v8::internal::CPURegister 143 reg_size = 0; 149 reg_size = r.reg_size; 156 reg_size = r.reg_size; 218 reg_size = 0; 224 reg_size = r.reg_size; 231 reg_size 1193 int reg_size = rd.SizeInBits(); local [all...] |
H A D | assembler-arm64-inl.h | 50 return reg_size; 57 return reg_size / 8; 63 return reg_size == 32; 69 return reg_size == 64; 86 ((reg_size == kWRegSizeInBits) || (reg_size == kXRegSizeInBits)) && 93 ((reg_size == kSRegSizeInBits) || (reg_size == kDRegSizeInBits)) && 101 DCHECK((reg_type != kNoRegister) || (reg_size == 0)); 109 return Aliases(other) && (reg_size 1026 ImmS(unsigned imms, unsigned reg_size) argument 1034 ImmR(unsigned immr, unsigned reg_size) argument 1043 ImmSetBits(unsigned imms, unsigned reg_size) argument 1052 ImmRotate(unsigned immr, unsigned reg_size) argument 1067 BitN(unsigned bitn, unsigned reg_size) argument [all...] |
H A D | disasm-arm64.cc | 231 unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSizeInBits local 233 if (rn_is_zr && !IsMovzMovnImm(reg_size, instr->ImmLogical())) { 256 bool DisassemblingDecoder::IsMovzMovnImm(unsigned reg_size, uint64_t value) { argument 257 DCHECK((reg_size == kXRegSizeInBits) || 258 ((reg_size == kWRegSizeInBits) && (value <= 0xffffffff))); 269 if ((reg_size == kXRegSizeInBits) && 276 if ((reg_size == kWRegSizeInBits) && 1510 unsigned reg_size = (instr->SixtyFourBits() == 1) ? kXRegSizeInBits local 1512 AppendToOutput("#%d", reg_size - r);
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H A D | macro-assembler-arm64.h | 260 static bool IsImmMovn(uint64_t imm, unsigned reg_size); 261 static bool IsImmMovz(uint64_t imm, unsigned reg_size); 262 static unsigned CountClearHalfWords(uint64_t imm, unsigned reg_size); 636 inline void PushSizeRegList(RegList registers, unsigned reg_size, argument 638 PushCPURegList(CPURegList(type, reg_size, registers)); 640 inline void PopSizeRegList(RegList registers, unsigned reg_size, argument 642 PopCPURegList(CPURegList(type, reg_size, registers));
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H A D | assembler-arm64.cc | 2359 unsigned reg_size = rd.SizeInBits(); local 2372 if (IsImmLogical(immediate, reg_size, &n, &imm_s, &imm_r)) { 2394 unsigned reg_size = rd.SizeInBits(); local 2396 Emit(SF(rd) | LogicalImmediateFixed | op | BitN(n, reg_size) | 2397 ImmSetBits(imm_s, reg_size) | ImmRotate(imm_r, reg_size) | dest_reg | 2485 unsigned reg_size = rd.SizeInBits(); local 2491 unsigned non_shift_bits = (reg_size - left_shift) & (reg_size - 1);
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H A D | macro-assembler-arm64.cc | 68 unsigned reg_size = rd.SizeInBits(); local 123 if (IsImmLogical(immediate, reg_size, &n, &imm_s, &imm_r)) { 186 unsigned reg_size = rd.SizeInBits(); local 197 if (CountClearHalfWords(~imm, reg_size) > 198 CountClearHalfWords(imm, reg_size)) { 210 DCHECK((reg_size % 16) == 0); 320 unsigned MacroAssembler::CountClearHalfWords(uint64_t imm, unsigned reg_size) { argument 321 DCHECK((reg_size % 8) == 0); 323 for (unsigned i = 0; i < (reg_size / 16); i++) { 335 bool MacroAssembler::IsImmMovz(uint64_t imm, unsigned reg_size) { argument 343 IsImmMovn(uint64_t imm, unsigned reg_size) argument 418 int reg_size = dst.SizeInBits(); local 440 int reg_size = dst.SizeInBits(); local [all...] |
/external/vixl/src/aarch64/ |
H A D | instructions-aarch64.cc | 51 static uint64_t RepeatBitsAcrossReg(unsigned reg_size, argument 56 VIXL_ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize)); 58 for (unsigned i = width; i < reg_size; i *= 2) { 128 unsigned reg_size = GetSixtyFourBits() ? kXRegSize : kWRegSize; local 167 return RepeatBitsAcrossReg(reg_size,
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H A D | debugger-aarch64.cc | 650 const uint64_t reg_size = target_reg.GetSizeInBits(); local 652 const uint64_t count = reg_size / format_size; 660 uint64_t data = reg_value >> (reg_size - (i * format_size));
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H A D | assembler-aarch64.h | 767 unsigned reg_size = rd.GetSizeInBits(); local 768 VIXL_ASSERT(shift < reg_size); 769 ubfm(rd, rn, (reg_size - shift) % reg_size, reg_size - shift - 1); 2704 static Instr ImmS(unsigned imms, unsigned reg_size) { argument 2705 VIXL_ASSERT(((reg_size == kXRegSize) && IsUint6(imms)) || 2706 ((reg_size == kWRegSize) && IsUint5(imms))); 2707 USE(reg_size); 2711 static Instr ImmR(unsigned immr, unsigned reg_size) { argument 2719 ImmSetBits(unsigned imms, unsigned reg_size) argument 2727 ImmRotate(unsigned immr, unsigned reg_size) argument 2740 BitN(unsigned bitn, unsigned reg_size) argument [all...] |
H A D | disasm-aarch64.cc | 264 unsigned reg_size = local 266 if (rn_is_zr && !IsMovzMovnImm(reg_size, instr->GetImmLogical())) { 292 bool Disassembler::IsMovzMovnImm(unsigned reg_size, uint64_t value) { argument 293 VIXL_ASSERT((reg_size == kXRegSize) || 294 ((reg_size == kWRegSize) && (value <= 0xffffffff))); 305 if ((reg_size == kXRegSize) && 312 if ((reg_size == kWRegSize) && (((value & 0xffff0000) == 0xffff0000) || 4241 unsigned reg_size = kXRegSize; local 4252 reg_size = kWRegSize; 4256 reg_size 4554 unsigned reg_size = local [all...] |
H A D | macro-assembler-aarch64.cc | 432 unsigned reg_size = rd.GetSizeInBits(); local 443 if (CountClearHalfWords(~imm, reg_size) > 444 CountClearHalfWords(imm, reg_size)) { 460 VIXL_ASSERT((reg_size % 16) == 0); 462 for (unsigned i = 0; i < (reg_size / 16); i++) { 500 int reg_size = dst.GetSizeInBits(); local 502 if (IsImmMovz(imm, reg_size) && !dst.IsSP()) { 509 } else if (IsImmMovn(imm, reg_size) && !dst.IsSP()) { 516 } else if (IsImmLogical(imm, reg_size, &n, &imm_s, &imm_r)) { 773 unsigned reg_size local 1526 int reg_size = dst.GetSizeInBits(); local 1925 int reg_size = registers.GetRegisterSizeInBytes(); local 1957 int reg_size = registers.GetRegisterSizeInBytes(); local 2256 const int reg_size = registers.GetRegisterSizeInBytes(); local 2307 int reg_size = registers.GetRegisterSizeInBytes(); local [all...] |
H A D | simulator-aarch64.cc | 298 uint64_t Simulator::AddWithCarry(unsigned reg_size, 304 VIXL_ASSERT((reg_size == kXRegSize) || (reg_size == kWRegSize)); 306 uint64_t max_uint = (reg_size == kWRegSize) ? kWMaxUInt : kXMaxUInt; 307 uint64_t reg_mask = (reg_size == kWRegSize) ? kWRegMask : kXRegMask; 308 uint64_t sign_mask = (reg_size == kWRegSize) ? kWSignMask : kXSignMask; 315 ReadNzcv().SetN(CalcNFlag(result, reg_size)); 337 int64_t Simulator::ShiftOperand(unsigned reg_size, argument 341 VIXL_ASSERT((reg_size == kWRegSize) || (reg_size 383 ExtendValue(unsigned reg_size, int64_t value, Extend extend_type, unsigned left_shift) const argument 471 GetPrintRegisterFormatForSize( unsigned reg_size, unsigned lane_size) argument 950 int reg_size = GetPrintRegSizeInBytes(format); local 1084 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local 1124 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local 1141 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local 1151 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local 1171 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local 1191 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local 1232 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local 1244 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local 1857 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local 1940 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local 2110 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local 2159 unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize; local 2213 unsigned reg_size = (instr->GetSixtyFourBits() == 1) ? kXRegSize : kWRegSize; local 3928 int reg_size = RegisterSizeInBytesFromFormat(vf); local [all...] |
H A D | macro-assembler-aarch64.h | 801 unsigned reg_size, 803 PushCPURegList(CPURegList(type, reg_size, registers)); 806 unsigned reg_size, 808 PopCPURegList(CPURegList(type, reg_size, registers)); 861 unsigned reg_size, 863 PeekCPURegList(CPURegList(type, reg_size, registers), offset); 868 unsigned reg_size, 870 PokeCPURegList(CPURegList(type, reg_size, registers), offset); 799 PushSizeRegList( RegList registers, unsigned reg_size, CPURegister::RegisterType type = CPURegister::kRegister) argument 805 PopSizeRegList(RegList registers, unsigned reg_size, CPURegister::RegisterType type = CPURegister::kRegister) argument 858 PeekSizeRegList( RegList registers, int64_t offset, unsigned reg_size, CPURegister::RegisterType type = CPURegister::kRegister) argument 865 PokeSizeRegList( RegList registers, int64_t offset, unsigned reg_size, CPURegister::RegisterType type = CPURegister::kRegister) argument
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/external/vixl/test/aarch64/ |
H A D | test-utils-aarch64.cc | 276 int reg_size, 285 r[i] = Register(n, reg_size); 307 int reg_size, 316 v[i] = FPRegister(n, reg_size); 273 PopulateRegisterArray(Register* w, Register* x, Register* r, int reg_size, int reg_count, RegList allowed) argument 304 PopulateFPRegisterArray(FPRegister* s, FPRegister* d, FPRegister* v, int reg_size, int reg_count, RegList allowed) argument
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H A D | test-simulator-aarch64.cc | 322 unsigned reg_size) { 323 VIXL_ASSERT((reg_size == kDRegSize) || (reg_size == kSRegSize)); 337 bool double_op = reg_size == kDRegSize; 455 unsigned reg_size) { 456 VIXL_ASSERT((reg_size == kDRegSize) || (reg_size == kSRegSize)); 471 bool double_op = reg_size == kDRegSize; 604 unsigned reg_size) { 605 VIXL_ASSERT((reg_size 318 Test2Op_Helper(Test2OpFPHelper_t helper, uintptr_t inputs, unsigned inputs_length, uintptr_t results, unsigned reg_size) argument 451 Test3Op_Helper(Test3OpFPHelper_t helper, uintptr_t inputs, unsigned inputs_length, uintptr_t results, unsigned reg_size) argument 600 TestCmp_Helper(TestFPCmpHelper_t helper, uintptr_t inputs, unsigned inputs_length, uintptr_t results, unsigned reg_size) argument 739 TestCmpZero_Helper(TestFPCmpZeroHelper_t helper, uintptr_t inputs, unsigned inputs_length, uintptr_t results, unsigned reg_size) argument [all...] |
H A D | test-assembler-aarch64.cc | 8121 int reg_size = sizeof(T) * 8; local 8122 Register left_reg(0, reg_size); 8123 Register right_reg(1, reg_size); 8124 Register result_reg(2, reg_size); 13908 // * Push <reg_count> registers with size <reg_size>. 13917 int reg_size, 13930 // Work out which registers to use, based on reg_size. 13934 PopulateRegisterArray(NULL, x, r, reg_size, reg_count, allowed); 13987 __ PushSizeRegList(list, reg_size); 14017 __ PopSizeRegList(list, reg_size); 13915 PushPopXRegSimpleHelper(int reg_count, int claim, int reg_size, PushPopMethod push_method, PushPopMethod pop_method) argument 14159 PushPopFPXRegSimpleHelper(int reg_count, int claim, int reg_size, PushPopMethod push_method, PushPopMethod pop_method) argument 14400 PushPopXRegMixedMethodsHelper(int claim, int reg_size) argument [all...] |
/external/jemalloc/src/ |
H A D | stats.c | 69 size_t reg_size, run_size, curregs; local 85 CTL_M2_GET("arenas.bin.0.size", j, ®_size, size_t); 159 reg_size, j, curregs * reg_size, nmalloc, 169 reg_size, j, curregs * reg_size, nmalloc,
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/external/jemalloc/include/jemalloc/internal/ |
H A D | arena.h | 248 * reg_interval has at least the same minimum alignment as reg_size; this 254 size_t reg_size; member in struct:arena_bin_info_s 259 /* Interval between regions (reg_size + (redzone_size << 1)). */
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/external/mesa3d/src/mesa/drivers/dri/i965/ |
H A D | brw_vs_emit.c | 1168 GLuint reg_size ) 1174 GLuint byte_offset = arg.nr * 32 + arg.subnr + offset * reg_size; 1187 brw_MUL(p, acc, vp_address, brw_imm_uw(reg_size)); 1190 brw_MUL(p, acc, suboffset(vp_address, 4), brw_imm_uw(reg_size)); 1208 int reg_size = 32; local 1225 brw_MUL(p, acc, vp_address, brw_imm_uw(reg_size)); 1229 brw_MUL(p, acc, suboffset(vp_address, 4), brw_imm_uw(reg_size)); 1231 brw_imm_uw(byte_offset + reg_size / 2));
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