Searched defs:temp2 (Results 1 - 17 of 17) sorted by relevance

/art/runtime/
H A Dcommon_dex_operations.h177 std::string temp1, temp2, temp3; local
181 field_class->GetDescriptor(&temp2),
H A Dclass_linker_test.cc283 std::string temp2; local
285 klass->GetDescriptor(&temp2)));
/art/runtime/interpreter/
H A Dinterpreter_switch_impl.cc310 std::string temp1, temp2; local
314 return_type->GetDescriptor(&temp2));
H A Dinterpreter_common.cc1037 std::string temp1, temp2; local
1042 arg_type->GetDescriptor(&temp2));
/art/runtime/mirror/
H A Dclass.cc384 std::string temp1, temp2; local
385 return IsInSamePackage(klass1->GetDescriptor(&temp1), klass2->GetDescriptor(&temp2));
/art/compiler/optimizing/
H A Dintrinsics_mips64.cc1710 GpuRegister temp2 = locations->GetTemp(1).AsRegister<GpuRegister>(); local
1750 __ Lw(temp2, arg, class_offset);
1751 __ Bnec(temp1, temp2, &return_false);
1756 __ Lw(temp2, arg, count_offset);
1759 __ Bnec(temp1, temp2, &return_false);
1775 __ Dext(temp2, temp1, 0, 1); // Extract compression flag.
1777 __ Sllv(temp1, temp1, temp2); // Double the byte count if uncompressed.
1784 __ Ld(temp2, temp3, value_offset);
1785 __ Bnec(out, temp2, &return_false);
H A Dintrinsics_arm.cc1132 Register temp2 = locations->GetTemp(2).AsRegister<Register>(); local
1166 __ ldr(temp2, Address(arg, count_offset));
1169 __ Lsr(temp1, temp2, 1u);
1185 __ eor(temp2, temp2, ShifterOperand(temp3));
1186 __ Lsrs(temp2, temp2, 1u);
1210 __ ldr(temp2, Address(arg, temp1));
1211 __ cmp(IP, ShifterOperand(temp2));
1216 __ ldr(temp2, Addres
1366 Register temp2 = locations->GetTemp(2).AsRegister<Register>(); local
1738 Register temp2 = temp2_loc.AsRegister<Register>(); local
2062 GenSystemArrayCopyBaseAddress(GetAssembler(), type, dest, dest_pos, temp2); local
2078 GenSystemArrayCopyBaseAddress(GetAssembler(), type, dest, dest_pos, temp2); local
[all...]
H A Dintrinsics_arm64.cc1275 Register temp2 = WRegisterFrom(locations->GetTemp(2)); local
1309 __ Ldr(temp2, HeapOperand(arg, count_offset));
1312 __ Lsr(temp1, temp2, 1u);
1327 __ Eor(temp2, temp2, Operand(temp3));
1331 __ Tbnz(temp2, 0, &different_compression); // Does not use flags.
1351 // Promote temp2 to an X reg, ready for LDR.
1352 temp2 = temp2.X();
1357 __ Ldr(temp2, MemOperan
1599 Register temp2 = XRegisterFrom(locations->GetTemp(0)); local
1632 Register temp2 = XRegisterFrom(locations->GetTemp(0)); local
2428 Register temp2 = WRegisterFrom(locations->GetTemp(1)); local
[all...]
H A Dintrinsics_arm_vixl.cc539 vixl32::Register temp2 = RegisterFrom(invoke->GetLocations()->GetTemp(0)); local
563 __ Vmov(temp2, op2);
565 __ Orr(temp1, temp1, temp2);
567 __ And(temp1, temp1, temp2);
822 vixl32::SRegister temp2 = HighSRegisterFrom(invoke->GetLocations()->GetTemp(0)); local
838 __ Vmov(temp2, 0.5);
840 __ Vcmp(F32, temp1, temp2);
1482 vixl32::Register temp2 = RegisterFrom(locations->GetTemp(2)); local
1516 __ Ldr(temp2, MemOperand(arg, count_offset));
1519 __ Lsr(temp1, temp2,
1746 vixl32::Register temp2 = RegisterFrom(locations->GetTemp(2)); local
2116 vixl32::Register temp2 = RegisterFrom(temp2_loc); local
2440 GenSystemArrayCopyBaseAddress(GetAssembler(), type, dest, dest_pos, temp2); local
2460 GenSystemArrayCopyBaseAddress(GetAssembler(), type, dest, dest_pos, temp2); local
[all...]
H A Dintrinsics_mips.cc2090 Register temp2 = locations->GetTemp(1).AsRegister<Register>(); local
2129 __ Lw(temp2, arg, class_offset);
2130 __ Bne(temp1, temp2, &return_false);
2135 __ Lw(temp2, arg, count_offset);
2138 __ Bne(temp1, temp2, &return_false);
2156 __ Ext(temp2, temp1, 0, 1);
2158 __ Sll(temp2, temp1, 31);
2159 __ Srl(temp2, temp2, 31);
2162 __ Sllv(temp1, temp1, temp2); // Doubl
[all...]
H A Dintrinsics_x86.cc109 Register temp2 = locations->GetTemp(1).AsRegister<Register>(); variable
113 // In this code path, registers `temp1`, `temp2`, and `temp3`
131 __ movl(temp2, Address(src, temp1, ScaleFactor::TIMES_4, adjusted_offset));
133 __ leal(temp2, Address(src_pos.AsRegister<Register>(), temp1, ScaleFactor::TIMES_1, 0));
134 __ movl(temp2, Address(src, temp2, ScaleFactor::TIMES_4, offset));
136 __ MaybeUnpoisonHeapReference(temp2);
144 DCHECK_NE(temp2, ESP);
145 DCHECK(0 <= temp2 && temp2 < kNumberOfCpuRegister
155 __ movl(Address(dest, temp1, ScaleFactor::TIMES_4, adjusted_offset), temp2); variable
158 __ movl(Address(dest, temp3, ScaleFactor::TIMES_4, offset), temp2); variable
222 XmmRegister temp2 = locations->GetTemp(1).AsFpuRegister<XmmRegister>(); local
2222 XmmRegister temp2 = locations->GetTemp(1).AsFpuRegister<XmmRegister>(); local
2356 Register temp2 = locations->GetTemp(1).AsRegister<Register>(); local
2983 Register temp2 = temp2_loc.AsRegister<Register>(); local
3307 GenSystemArrayCopyBaseAddress(GetAssembler(), type, dest, dest_pos, temp2); local
3325 GenSystemArrayCopyBaseAddress(GetAssembler(), type, dest, dest_pos, temp2); local
[all...]
H A Dintrinsics_x86_64.cc1188 CpuRegister temp2 = temp2_loc.AsRegister<CpuRegister>(); local
1292 // /* HeapReference<Class> */ temp2 = src->klass_
1295 // If heap poisoning is enabled, `temp1` and `temp2` have been
1301 // /* HeapReference<Class> */ temp2 = src->klass_
1302 __ movl(temp2, Address(src, class_offset));
1308 __ MaybeUnpoisonHeapReference(temp2);
1339 // /* HeapReference<Class> */ TMP = temp2->component_type_
1341 invoke, TMP_loc, temp2, component_offset, /* needs_null_check */ false);
1347 // /* HeapReference<Class> */ TMP = temp2->component_type_
1348 __ movl(CpuRegister(TMP), Address(temp2, component_offse
1420 GetAssembler(), type, src, src_pos, dest, dest_pos, length, temp1, temp2, temp3); local
2428 CpuRegister temp2 = locations->GetTemp(1).AsRegister<CpuRegister>(); local
2608 CpuRegister temp2 = locations->GetTemp(1).AsRegister<CpuRegister>(); local
[all...]
H A Dcode_generator_arm64.cc3013 Register temp2 = temps.AcquireSameSizeAs(array); local
3025 // /* HeapReference<Class> */ temp2 = value->klass_
3026 __ Ldr(temp2, HeapOperand(Register(value), class_offset));
3028 // nor `temp2`, as we are comparing two poisoned references.
3029 __ Cmp(temp, temp2);
3030 temps.Release(temp2);
3051 Register temp2 = temps.AcquireSameSizeAs(array); local
3053 __ Mov(temp2, value.W());
3054 GetAssembler()->PoisonHeapReference(temp2);
3055 source = temp2;
[all...]
H A Dcode_generator_arm.cc923 Register temp2,
932 temp2_(temp2) {
4100 Register temp2 = locations->GetTemp(1).AsRegister<Register>(); local
4108 __ smull(temp2, temp1, dividend, temp1);
4125 __ LoadImmediate(temp2, imm);
4126 __ mls(out, temp1, temp2, dividend);
5073 Register temp2,
5084 __ ldrexd(temp1, temp2, addr);
6069 Register temp2 = temp2_loc.AsRegister<Register>(); local
6115 // /* HeapReference<Class> */ temp2
915 LoadReferenceWithBakerReadBarrierAndUpdateFieldSlowPathARM(HInstruction* instruction, Location ref, Register obj, uint32_t offset, Location index, ScaleFactor scale_factor, bool needs_null_check, Register temp1, Register temp2, Location entrypoint) argument
5068 GenerateWideAtomicStore(Register addr, uint32_t offset, Register value_lo, Register value_hi, Register temp1, Register temp2, HInstruction* instruction) argument
8027 GenerateReferenceLoadWithBakerReadBarrier(HInstruction* instruction, Location ref, Register obj, uint32_t offset, Location index, ScaleFactor scale_factor, Location temp, bool needs_null_check, bool always_update_field, Register* temp2) argument
[all...]
H A Dcode_generator_arm_vixl.cc952 vixl32::Register temp2,
961 temp2_(temp2) {
4093 vixl32::Register temp2 = RegisterFrom(locations->GetTemp(1)); local
4102 __ Smull(temp2, temp1, dividend, temp1);
4119 __ Mov(temp2, imm);
4120 __ Mls(out, temp1, temp2, dividend);
5067 vixl32::Register temp2,
5084 __ ldrexd(temp1, temp2, MemOperand(addr));
6092 vixl32::Register temp2 = RegisterFrom(temp2_loc); local
6145 // /* HeapReference<Class> */ temp2
944 LoadReferenceWithBakerReadBarrierAndUpdateFieldSlowPathARMVIXL(HInstruction* instruction, Location ref, vixl32::Register obj, uint32_t offset, Location index, ScaleFactor scale_factor, bool needs_null_check, vixl32::Register temp1, vixl32::Register temp2, Location entrypoint) argument
5062 GenerateWideAtomicStore(vixl32::Register addr, uint32_t offset, vixl32::Register value_lo, vixl32::Register value_hi, vixl32::Register temp1, vixl32::Register temp2, HInstruction* instruction) argument
6684 vixl32::DRegister temp2 = temps.AcquireD(); local
8103 GenerateReferenceLoadWithBakerReadBarrier(HInstruction* instruction, Location ref, vixl32::Register obj, uint32_t offset, Location index, ScaleFactor scale_factor, Location temp, bool needs_null_check, bool always_update_field, vixl32::Register* temp2) argument
[all...]
H A Dcode_generator_x86.cc5003 XmmRegister temp2 = locations->GetTemp(1).AsFpuRegister<XmmRegister>(); local
5005 __ movd(temp2, value.AsRegisterPairHigh<Register>());
5006 __ punpckldq(temp1, temp2);
H A Dcode_generator_x86_64.cc559 CpuRegister temp2)
566 temp2_(temp2) {
6622 CpuRegister* temp2) {
6681 DCHECK(temp2 != nullptr);
6683 instruction, ref, obj, src, /* unpoison_ref_before_marking */ true, *temp1, *temp2);
553 ReadBarrierMarkAndUpdateFieldSlowPathX86_64(HInstruction* instruction, Location ref, CpuRegister obj, const Address& field_addr, bool unpoison_ref_before_marking, CpuRegister temp1, CpuRegister temp2) argument
6615 GenerateReferenceLoadWithBakerReadBarrier(HInstruction* instruction, Location ref, CpuRegister obj, const Address& src, bool needs_null_check, bool always_update_field, CpuRegister* temp1, CpuRegister* temp2) argument

Completed in 199 milliseconds