Searched defs:writemask (Results 1 - 25 of 31) sorted by relevance

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/external/mesa3d/src/gallium/drivers/r300/compiler/
H A Dradeon_opcodes.c524 unsigned int writemask,
537 if (!writemask)
542 srcmasks[src] |= writemask;
545 srcmasks[src] |= writemask;
522 rc_compute_sources_for_writemask( const struct rc_instruction *inst, unsigned int writemask, unsigned int *srcmasks) argument
H A Dradeon_rename_regs.c72 unsigned writemask; local
86 writemask = rc_variable_writemask_sum(var);
87 rc_variable_change_dst(var, new_index, writemask);
H A Dradeon_compiler.c168 * writemask is honoured.
170 void rc_move_output(struct radeon_compiler * c, unsigned output, unsigned new_output, unsigned writemask) argument
182 inst->U.I.DstReg.WriteMask &= writemask;
H A Dradeon_variable.c38 * Rewrite the index and writemask for the destination register of var
320 unsigned int writemask; local
334 writemask = sub_inst->WriteMask;
337 writemask = sub_inst->OutputWriteMask;
339 writemask = 0;
342 new_var = rc_variable(c, file, sub_inst->DestIndex, writemask,
392 unsigned int writemask = 0; local
394 writemask |= var->Dst.WriteMask;
397 return writemask;
H A Dradeon_pair_regalloc.c238 unsigned int writemask,
248 if (classes[i].Writemasks[j] == writemask) {
281 unsigned int writemask = rc_variable_writemask_sum(variable); local
293 writemask = RC_MASK_XYZW;
299 class_index = find_class(classes, writemask, 3);
314 writemask, c.Writemasks[i]);
321 * then the writemask will be set to RC_MASK_XYZW
379 class_index = find_class(classes, writemask,
388 variable->Dst.Index, writemask);
418 static int get_reg_id(unsigned int index, unsigned int writemask) argument
236 find_class( struct rc_class * classes, unsigned int writemask, unsigned int max_writemask_count) argument
615 unsigned int chan, class_id, writemask = 0; local
692 unsigned int writemask = reg_get_writemask(reg); local
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/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_wm_pass1.c42 if (inst->writemask & (1<<i)) {
44 inst->writemask &= ~(1<<i);
50 return inst->writemask;
123 GLuint writemask; local
144 writemask = get_tracked_mask(c, inst);
145 if (!writemask) {
166 read0 = writemask;
180 read0 = writemask;
181 read1 = writemask;
186 read0 = writemask;
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H A Dbrw_fs_vector_splitting.cpp273 unsigned int writemask; local
280 writemask = 1;
283 writemask = 1 << i;
296 NULL, writemask));
H A Dbrw_wm_pass0.c247 GLuint writemask )
253 if (writemask & (1<<i)) {
259 out->writemask = writemask;
317 GLuint writemask = inst->DstReg.WriteMask; local
341 pass0_set_dst(c, out, inst, writemask);
353 GLuint writemask = inst->DstReg.WriteMask; local
368 if (writemask & (1 << i)) {
H A Dbrw_eu.h90 GLuint writemask:4; /* dest only, align16 only */ member in struct:brw_reg::__anon15088::__anon15089
184 * \param writemask WRITEMASK_X/Y/Z/W bitfield
194 GLuint writemask )
217 * set swizzle and writemask to W, as the lower bits of subnr will
223 reg.dw1.bits.writemask = writemask;
531 /* If/else instructions break in align16 mode if writemask & swizzle
693 reg.dw1.bits.writemask &= mask;
701 reg.dw1.bits.writemask = mask;
967 GLuint writemask,
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H A Dbrw_vec4.cpp123 if (!(reg.writemask & (1 << i)))
152 this->writemask = WRITEMASK_XYZW;
169 int writemask)
176 this->writemask = writemask;
195 this->writemask = WRITEMASK_XYZW;
735 if (!(inst->dst.writemask & (1 << i)))
783 if (scan_inst->dst.writemask & (1 << i) &&
853 scan_inst->dst.writemask &= inst->dst.writemask;
168 dst_reg(register_file file, int reg, const glsl_type *type, int writemask) argument
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H A Dbrw_disasm.c278 char *writemask[16] = { variable
572 err |= control (file, "writemask", writemask, inst->bits1.da16.dest_writemask, NULL);
601 err |= control (file, "writemask", writemask, inst->bits1.da3src.dest_writemask, NULL);
H A Dbrw_vec4.h136 dst_reg(register_file file, int reg, const glsl_type *type, int writemask);
142 int writemask; /**< Bitfield of WRITEMASK_[XYZW] */ member in class:brw::dst_reg
H A Dbrw_eu_emit.c128 insn->bits1.da16.dest_writemask = dest.dw1.bits.writemask;
785 insn->bits1.da3src.dest_writemask = dest.dw1.bits.writemask;
2303 GLuint writemask,
2314 if (writemask == 0) {
2315 /*printf("%s: zero writemask??\n", __FUNCTION__); */
2325 * information and use it to modify the writemask for the
2329 if (writemask != WRITEMASK_XYZW) {
2334 if (writemask & (1<<i))
2339 if (!(writemask & (1<<i)))
2345 if (newmask != writemask) {
2297 brw_SAMPLE(struct brw_compile *p, struct brw_reg dest, GLuint msg_reg_nr, struct brw_reg src0, GLuint binding_table_index, GLuint sampler, GLuint writemask, GLuint msg_type, GLuint response_length, GLuint msg_length, GLuint header_present, GLuint simd_mode, GLuint return_format) argument
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H A Dbrw_wm.h144 GLuint writemask:4; member in struct:brw_wm_instruction
/external/mesa3d/src/glsl/
H A Dir_builder.cpp49 assign(deref lhs, operand rhs, int writemask) argument
55 NULL, writemask);
/external/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_state.h61 uint8_t writemask[2]; member in struct:si_state_dsa
/external/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_tgsi_aos.c327 LLVMValueRef writemask; local
329 writemask = lp_build_const_mask_aos_swizzled(bld->bld_base.base.gallivm,
335 mask = LLVMBuildAnd(builder, mask, writemask, "");
337 mask = writemask;
471 * assume a full writemask and then let LLVM optimization passes eliminate
/external/mesa3d/src/gallium/drivers/i915/
H A Di915_fpc_translate.c322 * Compute flags for saturation and writemask.
497 uint writemask; local
672 A0_DEST_CHANNEL_ALL, /* dest writemask */
687 A0_DEST_CHANNEL_ALL, /* dest writemask */
865 writemask = inst->Dst[0].Register.WriteMask;
867 if (writemask & TGSI_WRITEMASK_Y) {
870 if (writemask & TGSI_WRITEMASK_X)
889 if (writemask & TGSI_WRITEMASK_X) {
H A Di915_state.c446 int writemask = depth_stencil->stencil[0].writemask & 0xff; local
452 STENCIL_WRITE_MASK(writemask));
475 int wmask = depth_stencil->stencil[1].writemask & 0xff;
511 if (depth_stencil->depth.writemask)
/external/mesa3d/src/gallium/auxiliary/tgsi/
H A Dtgsi_text.c336 uint *writemask )
344 *writemask = TGSI_WRITEMASK_NONE;
348 *writemask |= TGSI_WRITEMASK_X;
352 *writemask |= TGSI_WRITEMASK_Y;
356 *writemask |= TGSI_WRITEMASK_Z;
360 *writemask |= TGSI_WRITEMASK_W;
363 if (*writemask == TGSI_WRITEMASK_NONE) {
371 *writemask = TGSI_WRITEMASK_XYZW;
683 uint writemask; local
696 if (!parse_opt_writemask( ctx, &writemask ))
1071 uint writemask; local
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H A Dtgsi_exec.c585 uint writemask = inst->Dst[0].Register.WriteMask; local
586 if (writemask == TGSI_WRITEMASK_X ||
587 writemask == TGSI_WRITEMASK_Y ||
588 writemask == TGSI_WRITEMASK_Z ||
589 writemask == TGSI_WRITEMASK_W ||
590 writemask == TGSI_WRITEMASK_NONE) {
/external/mesa3d/src/gallium/auxiliary/util/
H A Du_blit.c107 ctx->dsa_write_depth.depth.writemask = 1;
115 ctx->dsa_write_stencil.stencil[0].writemask = 0xff;
202 set_fragment_shader(struct blit_state *ctx, uint writemask, argument
205 if (!ctx->fs[pipe_tex][writemask]) {
208 ctx->fs[pipe_tex][writemask] =
211 writemask);
214 cso_set_fragment_shader_handle(ctx->cso, ctx->fs[pipe_tex][writemask]);
420 * \param writemask controls which channels in the dest surface are sourced
435 uint writemask, uint zs_writemask)
476 assert((writemask
425 util_blit_pixels(struct blit_state *ctx, struct pipe_resource *src_tex, unsigned src_level, int srcX0, int srcY0, int srcX1, int srcY1, int srcZ0, struct pipe_surface *dst, int dstX0, int dstY0, int dstX1, int dstY1, float z, uint filter, uint writemask, uint zs_writemask) argument
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/external/mesa3d/src/gallium/drivers/llvmpipe/
H A Dlp_bld_depth.c276 if (stencil[0].writemask != 0xff ||
277 (stencil[1].enabled && front_facing != NULL && stencil[1].writemask != 0xff)) {
278 /* mask &= stencil[0].writemask */
279 LLVMValueRef writemask = lp_build_const_int_vec(bld->gallivm, bld->type, local
280 stencil[0].writemask);
281 if (stencil[1].enabled && stencil[1].writemask != stencil[0].writemask && front_facing != NULL) {
283 stencil[1].writemask);
284 writemask = lp_build_select(bld, front_facing, writemask, back_writemas
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/external/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h600 // The writemask for AVX-512 instructions which is contained in EVEX.aaa
601 Reg writemask; member in struct:llvm::X86Disassembler::InternalInstruction
/external/mesa3d/src/gallium/drivers/r600/
H A Dr600_shader.c1767 static int tgsi_last_instruction(unsigned writemask) argument
1772 if (writemask & (1 << i)) {
3958 * muladd has no writemask, have to use another temp

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