/external/ltp/testcases/kernel/sched/hyperthreading/ht_affinity/ |
H A D | smt_smp_affinity.sh | 35 RC=0
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/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
H A D | SystemZInstrInfo.h | 77 const TargetRegisterClass *RC, 82 const TargetRegisterClass *RC,
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/external/llvm/include/llvm/IR/ |
H A D | InlineAsm.h | 290 static unsigned getFlagWordForRegClass(unsigned InputFlag, unsigned RC) { argument 291 // Store RC + 1, reserve the value 0 to mean 'no register class'. 292 ++RC; 293 assert(RC <= 0x7fff && "Too large register class ID"); 295 return InputFlag | (RC << 16); 347 /// class constraint. Sets RC to the register class ID. 348 static bool hasRegClassConstraint(unsigned Flag, unsigned &RC) { argument 353 // stores RC + 1. 356 RC = High - 1;
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | MachineRegisterInfo.cpp | 46 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { argument 47 VRegInfo[Reg].first = RC; 52 const TargetRegisterClass *RC, 55 if (OldRC == RC) 56 return RC; 57 const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC); 51 constrainRegClass(unsigned Reg, const TargetRegisterClass *RC, unsigned MinNumRegs) argument
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H A D | ExecutionDepsFix.cpp | 110 const TargetRegisterClass *const RC; member in class:__anon18521::ExeDepsFix 124 : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {} 457 assert(NumRegs == RC->getNumRegs() && "Bad regclass"); 462 for (TargetRegisterClass::const_iterator I = RC->begin(), E = RC->end(); 472 // Given a PhysReg, AliasMap[PhysReg] is either the relevant index into RC, 475 for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i) 476 for (const unsigned *AI = TRI->getOverlaps(RC->getRegister(i)); *AI; ++AI) 521 llvm::createExecutionDependencyFixPass(const TargetRegisterClass *RC) { [all...] |
H A D | TargetInstrInfoImpl.cpp | 248 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg); local 251 return RC->contains(LiveOp.getReg()) ? RC : 0; 253 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg))) 254 return RC; 313 const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]); local 314 if (!RC) 322 storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI); 324 loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI);
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H A D | VirtRegMap.cpp | 103 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) { argument 104 int SS = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(), 105 RC->getAlignment()); 133 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg); local 134 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC); 162 int VirtRegMap::getEmergencySpillSlot(const TargetRegisterClass *RC) { argument 164 EmergencySpillSlots.find(RC); 167 return EmergencySpillSlots[RC] = createSpillSlot(RC);
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/external/swiftshader/third_party/LLVM/utils/TableGen/ |
H A D | CodeGenRegisters.h | 138 // Returns true if RC is a subclass. 139 // RC is a sub-class of this class if it is a valid replacement for any 143 // 1. All RC registers are also in this. 144 // 2. The RC spill size must not be smaller than our spill size. 145 // 3. RC spill alignment must be compatible with ours. 147 bool hasSubClass(const CodeGenRegisterClass *RC) const { 148 return SubClasses.test(RC->EnumValue); 204 Key(const CodeGenRegisterClass &RC) argument 205 : Members(&RC.getMembers()), 206 SpillSize(RC [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | FastISel.h | 393 const TargetRegisterClass *RC); 398 const TargetRegisterClass *RC, unsigned Op0, 404 const TargetRegisterClass *RC, unsigned Op0, 410 const TargetRegisterClass *RC, unsigned Op0, 417 const TargetRegisterClass *RC, unsigned Op0, 423 const TargetRegisterClass *RC, unsigned Op0, 429 const TargetRegisterClass *RC, 435 const TargetRegisterClass *RC, unsigned Op0, 442 const TargetRegisterClass *RC, uint64_t Imm); 471 unsigned createResultReg(const TargetRegisterClass *RC); [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.cpp | 394 const TargetRegisterClass *RC, 406 if (RC == &SP::I64RegsRegClass) 409 else if (RC == &SP::IntRegsRegClass) 412 else if (RC == &SP::IntPairRegClass) 415 else if (RC == &SP::FPRegsRegClass) 418 else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) 421 else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) 433 const TargetRegisterClass *RC, 444 if (RC == &SP::I64RegsRegClass) 447 else if (RC 392 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 431 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86RegisterInfo.cpp | 93 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, argument 101 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx); 118 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC, argument 128 if (RC == &X86::GR8_NOREXRegClass) 129 return RC; 131 const TargetRegisterClass *Super = RC; 132 TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); 148 if (Super->getSize() == RC->getSize()) 153 return RC; 212 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) cons 223 getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const argument [all...] |
H A D | X86FastISel.cpp | 130 const TargetRegisterClass *RC); 358 const TargetRegisterClass *RC = nullptr; local 364 RC = &X86::GR8RegClass; 368 RC = &X86::GR16RegClass; 372 RC = &X86::GR32RegClass; 377 RC = &X86::GR64RegClass; 382 RC = &X86::FR32RegClass; 385 RC = &X86::RFP32RegClass; 391 RC = &X86::FR64RegClass; 394 RC 757 const TargetRegisterClass *RC = nullptr; local 1703 const TargetRegisterClass *RC = nullptr; local 1787 const TargetRegisterClass *RC; member in struct:DivRemEntry 1946 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); local 2122 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); local 2216 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); local 2244 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); local 2285 const TargetRegisterClass *RC = nullptr; local 2309 X86SelectFPExtOrFPTrunc(const Instruction *I, unsigned TargetOpc, const TargetRegisterClass *RC) argument 2462 const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::v8i16); local 2517 const TargetRegisterClass *RC = nullptr; local 2659 const TargetRegisterClass *RC; local 2965 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); local 3546 const TargetRegisterClass *RC = nullptr; local 3686 const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy(DL)); local 3700 const TargetRegisterClass *RC = nullptr; local [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
H A D | Thumb2InstrInfo.cpp | 122 const TargetRegisterClass *RC, 124 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass || 125 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass || 126 RC == ARM::GPRnopcRegisterClass) { 144 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI); 150 const TargetRegisterClass *RC, 152 if (RC == ARM::GPRRegisterClass || RC 120 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 148 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 134 const TargetRegisterClass *RC = nullptr; local 136 RC = TRI->getAllocatableClass( 140 UseRC = RC; 141 else if (RC) { 143 TRI->getCommonSubClass(UseRC, RC, VT.SimpleTy); 221 const TargetRegisterClass *RC = local 230 if (RC) 231 VTRC = TRI->getCommonSubClass(RC, VTRC); 233 RC = VTRC; 252 if (RegRC == RC) { 293 const TargetRegisterClass *RC = local [all...] |
/external/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyFastISel.cpp | 582 const TargetRegisterClass *RC; local 589 RC = &WebAssembly::I32RegClass; 593 RC = &WebAssembly::I64RegClass; 597 RC = &WebAssembly::F32RegClass; 601 RC = &WebAssembly::F64RegClass; 606 unsigned ResultReg = createResultReg(RC); 736 const TargetRegisterClass *RC; local 743 RC = &WebAssembly::I32RegClass; 747 RC = &WebAssembly::I64RegClass; 751 RC 983 const TargetRegisterClass *RC; local 1036 const TargetRegisterClass *RC; local [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 702 const TargetRegisterClass *RC = local 704 if (!RC) 708 if (!PPC::GPRCRegClass.hasSubClassEq(RC) && 709 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) && 710 !PPC::G8RCRegClass.hasSubClassEq(RC) && 711 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) 738 const TargetRegisterClass *RC = local 740 assert(RC && "TrueReg and FalseReg must have overlapping register classes"); 742 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) || 743 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC); 956 StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs, bool &NonRI, bool &SpillsVRS) const argument 1058 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 1091 LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr *> &NewMIs, bool &NonRI, bool &SpillsVRS) const argument 1167 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument [all...] |
/external/llvm/lib/Target/AMDGPU/ |
H A D | SIInsertWaits.cpp | 106 RegInterval getRegInterval(const TargetRegisterClass *RC, 204 const TargetRegisterClass *RC = TII->getOpRegClass(MI, 0); local 205 unsigned Size = RC->getSize(); 275 RegInterval SIInsertWaits::getRegInterval(const TargetRegisterClass *RC, argument 277 unsigned Size = RC->getSize(); 341 const TargetRegisterClass *RC = TII->getOpRegClass(*I, i); local 342 RegInterval Interval = getRegInterval(RC, Op); 471 const TargetRegisterClass *RC = TII->getOpRegClass(MI, i); local 472 RegInterval Interval = getRegInterval(RC, Op);
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H A D | SIRegisterInfo.cpp | 708 bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const { 709 switch (RC->getSize()) { 713 return getCommonSubClass(&AMDGPU::VGPR_32RegClass, RC) != nullptr; 715 return getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) != nullptr; 717 return getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) != nullptr; 719 return getCommonSubClass(&AMDGPU::VReg_128RegClass, RC) != nullptr; 721 return getCommonSubClass(&AMDGPU::VReg_256RegClass, RC) != nullptr; 723 return getCommonSubClass(&AMDGPU::VReg_512RegClass, RC) != nullptr; 768 const TargetRegisterClass *RC, unsigned SubIdx) const { 770 return RC; 767 getSubRegClass( const TargetRegisterClass *RC, unsigned SubIdx) const argument 880 const TargetRegisterClass *RC = getPhysRegClass(Reg); local 1007 const TargetRegisterClass *RC; local [all...] |
/external/autotest/client/site_tests/firmware_TouchMTB/ |
H A D | firmware_constants.py | 208 RC = _RobotControl() variable 209 RC.PAUSE_TYPE = 'pause_type' 210 RC.PROMPT = 'finger_control_prompt' 214 RC.PER_GESTURE = 'per_gesture' 218 RC.PER_VARIATION = 'per_variation'
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/external/ltp/testcases/commands/mail/ |
H A D | mail_tests.sh | 61 RC=0 96 # Set return code RC variable to 0, it will be set with a non-zero return code 100 RC=0 229 RC=0 299 RC=0 335 RC=0
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 334 const TargetRegisterClass *RC, 337 if (PPC::GPRCRegisterClass->hasSubClassEq(RC)) { 353 } else if (PPC::G8RCRegisterClass->hasSubClassEq(RC)) { 369 } else if (PPC::F8RCRegisterClass->hasSubClassEq(RC)) { 374 } else if (PPC::F4RCRegisterClass->hasSubClassEq(RC)) { 379 } else if (PPC::CRRCRegisterClass->hasSubClassEq(RC)) { 417 } else if (PPC::CRBITRCRegisterClass->hasSubClassEq(RC)) { 451 } else if (PPC::VRRCRegisterClass->hasSubClassEq(RC)) { 474 const TargetRegisterClass *RC, 479 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMI 331 StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const argument 471 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 498 LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const argument 596 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonFrameLowering.cpp | 1091 const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg); local 1092 HII.storeRegToStackSlot(MBB, MI, Reg, IsKill, FI, RC, &HRI); 1144 const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg); local 1146 HII.loadRegFromStackSlot(MBB, MI, Reg, FI, RC, &HRI); 1205 /// Returns true if there are no caller-saved registers available in class RC. 1207 const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC) { 1219 for (const MCPhysReg *P = HRI.getCallerSavedRegs(&MF, RC); *P; ++P) 1323 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(S->Reg); local 1324 int FI = MFI->CreateFixedSpillStackObject(RC->getSize(), S->Offset); 1335 const TargetRegisterClass *RC local 1206 needToReserveScavengingSpillSlots(MachineFunction &MF, const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC) argument 1473 auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass local 1513 auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass local 1558 auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass local 1611 auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass local 1660 auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass local 1697 auto *RC = !Is128B ? &Hexagon::VectorRegsRegClass local 1876 const TargetRegisterClass *RC; member in struct:SlotInfo 1950 const TargetRegisterClass *RC = nullptr; local 2112 auto *RC = getRegClass({SrcOp.getReg(), SrcOp.getSubReg()}); local [all...] |
/external/clang/test/Layout/ |
H A D | ms-x86-pack-and-align.cpp | 434 struct RC { struct 440 RC c; 472 // CHECK-NEXT: 0 | struct RC 480 // CHECK-NEXT: 1 | struct RC c 513 // CHECK-X64-NEXT: 0 | struct RC 521 // CHECK-X64-NEXT: 1 | struct RC c 798 sizeof(RC)+
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/external/llvm/lib/CodeGen/GlobalISel/ |
H A D | RegisterBankInfo.cpp | 178 const TargetRegisterClass *RC = local 180 if (RC) 181 return &getRegBankFromRegClass(*RC); 190 const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, &TRI); local 192 if (!RC) 195 const RegisterBank &RegBank = getRegBankFromRegClass(*RC); 197 assert(RegBank.covers(*RC) && 365 const TargetRegisterClass *RC = nullptr; local 370 RC = TRI.getMinimalPhysRegClass(Reg); 378 RC [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.h | 125 getCrossCopyRegClass(const TargetRegisterClass *RC) const override; 128 getLargestLegalSuperClass(const TargetRegisterClass *RC, 131 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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