Searched refs:RC (Results 201 - 225 of 458) sorted by relevance

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/external/llvm/lib/Analysis/
H A DLazyCallGraph.cpp1166 RefSCC &RC = *Result[SCCNumber - 1];
1167 int SCCIndex = RC.SCCs.size();
1168 RC.SCCs.push_back(C);
1170 C->OuterRefSCC = &RC;
1177 for (RefSCC *RC : Result)
1178 G->connectRefSCC(*RC);
1282 void LazyCallGraph::buildSCCs(RefSCC &RC, node_stack_range Nodes) {
1283 assert(RC.SCCs.empty() && "Already built SCCs!");
1284 assert(RC.SCCIndices.empty() && "Already mapped SCC indices!");
1381 RC
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/external/clang/test/SemaCXX/
H A Dnested-name-spec.cpp71 struct RC;
77 struct A2::RC { struct in class:A2
103 void f6(int A2::RC::x); // expected-error{{parameter declarator cannot be qualified}}
105 int A2::RC::x; // expected-error{{non-static data member defined out-of-line}}
/external/llvm/lib/CodeGen/
H A DCriticalAntiDepBreaker.h101 const TargetRegisterClass *RC,
H A DRegAllocFast.cpp171 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
205 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) { argument
212 int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
213 RC->getAlignment());
291 const TargetRegisterClass *RC = MRI->getRegClass(LRI->VirtReg); local
292 int FI = getStackSpaceFor(LRI->VirtReg, RC);
294 TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI);
532 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg); local
536 !RC->contains(Hint) || !MRI->isAllocatable(Hint)))
552 ArrayRef<MCPhysReg> AO = RegClassInfo.getOrder(RC);
644 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg); local
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/external/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DSIMCCodeEmitter.cpp214 const MCRegisterClass &RC = MRI.getRegClass(RCID); local
218 if (getLitEncoding(Op, RC.getSize()) != 255)
284 const MCRegisterClass &RC = MRI.getRegClass(RCID); local
286 uint32_t Enc = getLitEncoding(MO, RC.getSize());
/external/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp127 const TargetRegisterClass *RC,
138 if (RC == &ARM::GPRRegClass || RC == &ARM::tGPRRegClass ||
139 RC == &ARM::tcGPRRegClass || RC == &ARM::rGPRRegClass ||
140 RC == &ARM::GPRnopcRegClass) {
147 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
164 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
170 const TargetRegisterClass *RC,
180 if (RC
125 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
168 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/llvm/lib/Target/Mips/
H A DMipsMachineFunction.h82 int getMoveF64ViaSpillFI(const TargetRegisterClass *RC);
H A DMipsOptimizePICCall.cpp119 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg); local
120 assert(RC->vt_end() - RC->vt_begin() == 1);
121 return *RC->vt_begin();
H A DMipsRegisterInfo.h47 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h73 const TargetRegisterClass *RC,
78 const TargetRegisterClass *RC,
191 const TargetRegisterClass *RC,
197 const TargetRegisterClass *RC,
/external/llvm/utils/TableGen/
H A DCodeGenIntrinsics.h118 std::vector<CodeGenIntrinsic> LoadIntrinsics(const RecordKeeper &RC,
/external/ltp/testcases/kernel/controllers/cpuctl/
H A Drun_cpuctl_stress_test.sh55 RC=0; # return code from functions
365 RC=$?; # Return status of the task being waited
368 if [ $RC -ne 0 ]
370 echo "Task $i exited abnormaly with return value: $RC";
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
H A DPasses.h233 /// The pass will examine instructions using and defining registers in RC.
235 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DCriticalAntiDepBreaker.h106 const TargetRegisterClass *RC);
H A DVirtRegRewriter.cpp417 unsigned GetRegForReload(const TargetRegisterClass *RC, unsigned PhysReg,
445 const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(VirtReg); local
446 return GetRegForReload(RC, PhysReg, MF, MI, Spills, MaybeDeadStores,
705 static unsigned findSuperReg(const TargetRegisterClass *RC, unsigned SubReg,
707 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
787 const TargetRegisterClass* RC = TRI->getMinimalPhysRegClass(Reg);
791 if (!TII->isSafeToMoveRegClassDefs(RC))
865 unsigned ReuseInfo::GetRegForReload(const TargetRegisterClass *RC,
888 RC
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H A DRegAllocLinearScan.cpp267 const TargetRegisterClass *RC);
354 const TargetRegisterClass *RC,
361 unsigned getFirstNonReservedPhysReg(const TargetRegisterClass *RC) { argument
362 ArrayRef<unsigned> O = RegClassInfo.getOrder(RC);
489 const TargetRegisterClass *RC = mri_->getRegClass(cur.reg); local
490 if (!RC->contains(CandReg))
773 const TargetRegisterClass *RC) {
784 RC->contains(*as)) {
967 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg); local
969 << RC
771 updateSpillWeights(std::vector<float> &Weights, unsigned reg, float weight, const TargetRegisterClass *RC) argument
1419 getFreePhysReg(LiveInterval* cur, const TargetRegisterClass *RC, unsigned MaxInactiveCount, SmallVector<unsigned, 256> &inactiveCounts, bool SkipDGRegs) argument
1503 const TargetRegisterClass *RC = mri_->getRegClass(cur->reg); local
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H A DPrologEpilogInserter.cpp253 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg); local
270 unsigned Align = RC->getAlignment();
277 FrameIdx = MFI->CreateStackObject(RC->getSize(), Align, true);
282 FrameIdx = MFI->CreateFixedObject(RC->getSize(), FixedSlot->Offset, true);
321 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); local
323 CSI[i].getFrameIdx(), RC, TRI);
348 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); local
351 RC, TRI);
396 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); local
400 RC, TR
447 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); local
849 const TargetRegisterClass *RC = Fn.getRegInfo().getRegClass(Reg); local
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H A DRegAllocFast.cpp150 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
176 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) { argument
183 int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
184 RC->getAlignment());
266 const TargetRegisterClass *RC = MRI->getRegClass(LRI->first); local
267 int FI = getStackSpaceFor(LRI->first, RC);
269 TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI);
485 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg); local
489 !RC->contains(Hint) || !RegClassInfo.isAllocatable(Hint)))
503 ArrayRef<unsigned> AO = RegClassInfo.getOrder(RC);
586 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg); local
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/external/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp343 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass local
346 unsigned ResultReg = createResultReg(RC);
376 const TargetRegisterClass *RC = Is64Bit ? local
379 unsigned TmpReg = createResultReg(RC);
1252 const TargetRegisterClass *RC = local
1256 ResultReg = createResultReg(RC);
1294 const TargetRegisterClass *RC; local
1296 RC = Is64Bit ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
1298 RC = Is64Bit ? &AArch64::GPR64spRegClass : &AArch64::GPR32spRegClass;
1301 ResultReg = createResultReg(RC);
1337 const TargetRegisterClass *RC = local
1377 const TargetRegisterClass *RC = nullptr; local
1614 const TargetRegisterClass *RC; local
1666 const TargetRegisterClass *RC; local
1766 const TargetRegisterClass *RC; local
2585 const TargetRegisterClass *RC; local
2891 const TargetRegisterClass *RC; local
3878 const TargetRegisterClass *RC = local
3917 const TargetRegisterClass *RC = local
3945 const TargetRegisterClass *RC = local
4023 const TargetRegisterClass *RC = local
4052 const TargetRegisterClass *RC = local
4144 const TargetRegisterClass *RC = local
4173 const TargetRegisterClass *RC = local
4296 const TargetRegisterClass *RC = local
4488 const TargetRegisterClass *RC = local
4684 const TargetRegisterClass *RC = nullptr; local
4780 const TargetRegisterClass *RC; local
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H A DAArch64AsmPrinter.cpp95 const TargetRegisterClass *RC, bool isVector,
225 // Prints the register in MO using class RC using the offset in the
229 const TargetRegisterClass *RC,
234 unsigned RegToPrint = RC->getRegister(RI->getEncodingValue(Reg));
275 const TargetRegisterClass *RC; local
278 RC = &AArch64::FPR8RegClass;
281 RC = &AArch64::FPR16RegClass;
284 RC = &AArch64::FPR32RegClass;
287 RC = &AArch64::FPR64RegClass;
290 RC
228 printAsmRegInClass(const MachineOperand &MO, const TargetRegisterClass *RC, bool isVector, raw_ostream &O) argument
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DARMBaseRegisterInfo.cpp250 ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC, argument
254 unsigned Size = RC->getSize() * 8;
366 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
368 const TargetRegisterClass *Super = RC;
369 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
382 return RC;
391 ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
392 if (RC == &ARM::CCRRegClass)
394 return RC;
398 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, argument
420 getRawAllocationOrder(const TargetRegisterClass *RC, unsigned HintType, unsigned HintReg, const MachineFunction &MF) const argument
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/external/swiftshader/third_party/LLVM/lib/Target/X86/
H A DX86InstrInfo.h228 const TargetRegisterClass *RC,
233 const TargetRegisterClass *RC,
241 const TargetRegisterClass *RC,
246 const TargetRegisterClass *RC,
330 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
/external/pcre/dist2/src/sljit/
H A DsljitNativePPC_64.c203 return push_inst(compiler, NOR | RC(flags) | S(src2) | A(dst) | B(src2));
213 return push_inst(compiler, CNTLZW | RC(flags) | S(src2) | A(dst));
214 return push_inst(compiler, CNTLZD | RC(flags) | S(src2) | A(dst));
307 return push_inst(compiler, AND | RC(flags) | S(src1) | A(dst) | B(src2));
323 return push_inst(compiler, OR | RC(flags) | S(src1) | A(dst) | B(src2));
339 return push_inst(compiler, XOR | RC(flags) | S(src1) | A(dst) | B(src2));
346 return push_inst(compiler, RLWINM | RC(flags) | S(src1) | A(dst) | (compiler->imm << 11) | ((31 - compiler->imm) << 1));
350 return push_inst(compiler, RLDI(dst, src1, compiler->imm, 63 - compiler->imm, 1) | RC(flags));
353 return push_inst(compiler, ((flags & ALT_FORM2) ? SLW : SLD) | RC(flags) | S(src1) | A(dst) | B(src2));
360 return push_inst(compiler, RLWINM | RC(flag
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp592 const TargetRegisterClass *RC = TLI.getRegClassFor(VT); local
593 unsigned ResultReg = createResultReg(RC);
616 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT); local
617 unsigned ResultReg = createResultReg(RC);
1098 unsigned FastISel::createResultReg(const TargetRegisterClass* RC) { argument
1099 return MRI.createVirtualRegister(RC);
1103 const TargetRegisterClass* RC) {
1104 unsigned ResultReg = createResultReg(RC);
1112 const TargetRegisterClass *RC,
1114 unsigned ResultReg = createResultReg(RC);
1102 FastEmitInst_(unsigned MachineInstOpcode, const TargetRegisterClass* RC) argument
1111 FastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill) argument
1130 FastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument
1151 FastEmitInst_rrr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) argument
1175 FastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument
1196 FastEmitInst_rii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm1, uint64_t Imm2) argument
1219 FastEmitInst_rf(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, const ConstantFP *FPImm) argument
1240 FastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument
1264 FastEmitInst_i(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm) argument
1280 FastEmitInst_ii(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm1, uint64_t Imm2) argument
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/external/llvm/lib/Transforms/Scalar/
H A DGuardWidening.cpp452 for (auto &RC : CombinedChecks) {
453 makeAvailableAt(RC.getCheckInst(), InsertPt);
455 Result = BinaryOperator::CreateAnd(RC.getCheckInst(), Result, "",
458 Result = RC.getCheckInst();
566 auto IsCurrentCheck = [&](GuardWideningImpl::RangeCheck &RC) {
567 return RC.getBase() == CurrentBase && RC.getLength() == CurrentLength;
603 auto OffsetOK = [&](const GuardWideningImpl::RangeCheck &RC) {
604 return (HighOffset - RC.getOffsetValue()).ult(MaxDiff);

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