Searched refs:RC (Results 51 - 75 of 458) sorted by relevance

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/external/llvm/lib/Target/Hexagon/
H A DHexagonBitTracker.cpp82 const TargetRegisterClass *RC = MRI.getRegClass(Reg); local
83 unsigned ID = RC->getID();
205 auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW)
207 assert(RW <= RC.width());
208 return eXTR(RC, 0, RW);
211 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW)
213 uint16_t W = RC.width();
215 return eXTR(RC, W-RW, W);
218 auto half = [this] (const BT::RegisterCell &RC, unsigned N)
220 assert(N*16+16 <= RC
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/external/swiftshader/third_party/LLVM/lib/Target/
H A DTargetRegisterInfo.cpp62 const TargetRegisterClass* RC = *I; local
63 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
64 (!BestRC || BestRC->hasSubClass(RC)))
65 BestRC = RC;
75 const TargetRegisterClass *RC, BitVector &R){
76 ArrayRef<unsigned> Order = RC->getRawAllocationOrder(MF);
82 const TargetRegisterClass *RC) const {
84 if (RC) {
85 getAllocatableSetForRC(MF, RC, Allocatabl
74 getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R) argument
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/external/ltp/testcases/kernel/power_management/
H A Dpm_include.sh105 RC=0
114 RC=1
119 RC=1
123 return $RC
178 RC=0
187 RC=1
194 RC=1
205 RC=1
214 return $RC
231 RC
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/external/ltp/
H A Dltpmenu110 you wish to continue ??" 7 70 || RC=$?
111 case $RC in
164 RC=0
168 while [ $RC -ne "1" ]
175 2>/tmp/runltp.results.$$ || RC=$?
223 RC=$?
224 if [ $RC -eq "0" ]
241 RC=$?
242 if [ $RC -eq "0" ]
282 RC
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/external/swiftshader/third_party/LLVM/utils/release/
H A Dtest-release.sh28 RC=""
61 -rc | --rc | -RC | --RC )
63 RC=$1
115 if [ -z "$RC" ]; then
135 BuildDir=$BuildDir/rc$RC
152 if ! svn ls $Base_url/$proj/tags/RELEASE_$Release_no_dot/rc$RC > /dev/null 2>&1 ; then
153 echo "llvm $Release release candidate $RC doesn't exist!"
164 echo "# Exporting $proj $Release-RC$RC source
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/external/ltp/testscripts/
H A Dtpm_tools.sh53 RC=0
69 RC=1
82 RC=1
90 RC=1
103 RC=1
110 RC=1
124 RC=1
132 RC=1
144 RC=1
154 if [ $RC
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/external/ltp/testcases/commands/cron/
H A Dcron_tests.sh71 # Set return code RC variable to 0, it will be set with a non-zero return code
76 RC=0
114 RC=$?
116 if [ $RC -ne 0 ]
129 RC=$?
133 if [ "$RC" -ne 0 -a -f /var/log/cron ]; then
137 RC=$?
139 if [ $RC -ne 0 ]
226 RC=$?
230 if [ "$RC"
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/external/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h93 bool isSGPRClass(const TargetRegisterClass *RC) const {
94 return !hasVGPRs(RC);
103 const TargetRegisterClass *RC; local
105 RC = MRI.getRegClass(Reg);
107 RC = getPhysRegClass(Reg);
108 return isSGPRClass(RC);
112 bool hasVGPRs(const TargetRegisterClass *RC) const;
117 static bool isPseudoRegClass(const TargetRegisterClass *RC) { argument
118 return RC == &AMDGPU::VS_32RegClass || RC
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/external/llvm/unittests/Analysis/
H A DLazyCallGraphTest.cpp347 LazyCallGraph::RefSCC &RC = *I++; local
351 auto J = RC.begin();
392 EXPECT_EQ(RC.end(), J);
431 LazyCallGraph::RefSCC &RC = *I++; local
439 EXPECT_EQ(&RC, CG.lookupRefSCC(N1));
440 EXPECT_EQ(&RC, CG.lookupRefSCC(N2));
441 EXPECT_EQ(&RC, CG.lookupRefSCC(N3));
442 EXPECT_EQ(&RC, CG.lookupRefSCC(N4));
443 EXPECT_EQ(&RC, CG.lookupRefSCC(N5));
445 ASSERT_EQ(1, RC
771 LazyCallGraph::RefSCC &RC = *I++; local
859 LazyCallGraph::RefSCC &RC = *I++; local
917 LazyCallGraph::RefSCC &RC = *I++; local
1004 LazyCallGraph::RefSCC &RC = *I++; local
1116 LazyCallGraph::RefSCC &RC = *I++; local
1246 LazyCallGraph::RefSCC &RC = *I++; local
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/external/llvm/lib/CodeGen/
H A DTargetRegisterInfo.cpp111 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
112 if (!RC || RC->isAllocatable())
113 return RC;
115 for (BitMaskClassIterator It(RC->getSubClassMask(), *this); It.isValid();
135 const TargetRegisterClass* RC = *I;
136 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
137 (!BestRC || BestRC->hasSubClass(RC)))
138 BestRC = RC;
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/external/swiftshader/third_party/LLVM/include/llvm/Target/
H A DTargetRegisterInfo.h142 bool hasSubClass(const TargetRegisterClass *RC) const {
143 return RC != this && hasSubClassEq(RC);
146 /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this
148 bool hasSubClassEq(const TargetRegisterClass *RC) const {
149 unsigned ID = RC->getID();
155 bool hasSuperClass(const TargetRegisterClass *RC) const {
156 return RC->hasSubClass(this);
159 /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this
161 bool hasSuperClassEq(const TargetRegisterClass *RC) cons
396 canCombineSubRegIndices(const TargetRegisterClass *RC, SmallVectorImpl<unsigned> &SubIndices, unsigned &NewSubIdx) const argument
648 saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const argument
[all...]
/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DAllocationOrder.cpp29 const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg); local
45 TRI.getRawAllocationOrder(RC, HintPair.first, Hint,
65 ArrayRef<unsigned> O = RCI.getOrder(RC);
72 !RC->contains(Hint) || RCI.isReserved(Hint)))
H A DRegisterClassInfo.cpp67 /// compute - Compute the preferred allocation order for RC with reserved
70 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
71 RCInfo &RCI = RegClass[RC->getID()];
74 unsigned NumRegs = RC->getNumRegs();
84 ArrayRef<unsigned> RawOrder = RC->getRawAllocationOrder(*MF);
102 // Check if RC is a proper sub-class.
103 if (const TargetRegisterClass *Super = TRI->getLargestLegalSuperClass(RC))
104 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
108 dbgs() << "AllocationOrder(" << RC->getName() << ") = [";
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
H A DBlackfinInstrInfo.h58 const TargetRegisterClass *RC,
64 const TargetRegisterClass *RC,
70 const TargetRegisterClass *RC,
75 const TargetRegisterClass *RC,
H A DBlackfinInstrInfo.cpp162 const TargetRegisterClass *RC) {
166 return Test.hasSubClassEq(RC);
175 const TargetRegisterClass *RC,
179 if (inClass(BF::DPRegClass, SrcReg, RC)) {
187 if (inClass(BF::D16RegClass, SrcReg, RC)) {
195 if (inClass(BF::AnyCCRegClass, SrcReg, RC)) {
204 RC->getName()).c_str());
212 const TargetRegisterClass *RC,
222 const TargetRegisterClass *RC,
225 if (inClass(BF::DPRegClass, DestReg, RC)) {
160 inClass(const TargetRegisterClass &Test, unsigned Reg, const TargetRegisterClass *RC) argument
170 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
208 storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const argument
218 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
250 loadRegFromAddr(MachineFunction &MF, unsigned DestReg, SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const argument
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
H A DX86RegisterInfo.h78 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const;
81 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
91 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
93 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
/external/ltp/testcases/commands/tar/
H A Dtar_tests.sh48 # set return code RC variable to 0, it will be set with a non-zero return code
53 RC=0
71 $LTPTMP/tar_tstf2 $LTPTMP/tar_tstf3 > $LTPTMP/tar_tst.out 2>&1 || RC=$?
73 if [ $RC -eq 0 ]; then
102 $LTPTMP/tar_tstf2 $LTPTMP/tar_tstf3 > $LTPTMP/tar_tst.out 2>&1 || RC=$?
104 if [ $RC -eq 0 ]; then
119 tar -tvf $LTPTMP/tar_tstf.tar > /$LTPTMP/tar_tst.out 2>&1 || RC=$?
121 if [ $RC -eq 0 ]; then
149 $LTPTMP/tar_tstf2 $LTPTMP/tar_tstf3 > $LTPTMP/tar_tst.out 2>&1 || RC=$?
151 if [ $RC
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/external/llvm/include/llvm/Target/
H A DTargetRegisterInfo.h144 bool hasSubClass(const TargetRegisterClass *RC) const {
145 return RC != this && hasSubClassEq(RC);
148 /// Returns true if RC is a sub-class of or equal to this class.
149 bool hasSubClassEq(const TargetRegisterClass *RC) const {
150 unsigned ID = RC->getID();
156 bool hasSuperClass(const TargetRegisterClass *RC) const {
157 return RC->hasSubClass(this);
160 /// Returns true if RC is a super-class of or equal to this class.
161 bool hasSuperClassEq(const TargetRegisterClass *RC) cons
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/external/llvm/utils/release/
H A Dtest-release.sh27 RC=""
79 -rc | --rc | -RC | --RC )
81 RC="rc$1"
84 RC=final
91 RC="`echo $ExportBranch | sed -e 's,/,_,g'`"
181 if [ -z "$RC" ]; then
186 ExportBranch="tags/RELEASE_$Release_no_dot/$RC"
231 BuildDir=$BuildDir/$RC
241 if [ $RC !
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/external/swiftshader/third_party/LLVM/utils/TableGen/
H A DRegisterInfoEmitter.cpp340 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; local
341 ArrayRef<Record*> Order = RC.getOrder();
344 std::string Name = RC.getName();
373 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; local
374 OS << " MCRegisterClass(" << RC.getQualifiedName() + "RegClassID" << ", "
375 << '\"' << RC.getName() << "\", "
376 << RC.SpillSize/8 << ", "
377 << RC.SpillAlignment/8 << ", "
378 << RC.CopyCost << ", "
379 << RC
455 const CodeGenRegisterClass &RC = *RegisterClasses[i]; local
503 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; local
514 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; local
548 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; local
561 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; local
592 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; local
604 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; local
620 const CodeGenRegisterClass &RC = *RegisterClasses[i]; local
800 const CodeGenRegisterClass &RC = *RegisterClasses[rci]; local
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/external/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp133 for (const auto &RC : RegisterClasses)
134 OS << " " << RC.getName() << "RegClassID"
135 << " = " << RC.EnumValue << ",\n";
197 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
199 for (const auto &RC : RegBank.getRegClasses()) {
200 const CodeGenRegister::Vec &Regs = RC.getMembers();
205 RC.buildRegUnitSet(RegUnits);
209 OS << "}, \t// " << RC.getName() << "\n";
212 << " return RCWeightTable[RC->getID()];\n"
308 << "getRegClassPressureSets(const TargetRegisterClass *RC) cons
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DThumb1InstrInfo.cpp48 const TargetRegisterClass *RC,
50 assert((RC == ARM::tGPRRegisterClass ||
54 if (RC == ARM::tGPRRegisterClass ||
77 const TargetRegisterClass *RC,
79 assert((RC == ARM::tGPRRegisterClass ||
83 if (RC == ARM::tGPRRegisterClass ||
46 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
75 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
/external/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.h47 const TargetRegisterClass *RC,
53 const TargetRegisterClass *RC,
/external/llvm/lib/Target/NVPTX/
H A DNVPTXRegisterInfo.h60 std::string getNVPTXRegClassName(const TargetRegisterClass *RC);
61 std::string getNVPTXRegClassStr(const TargetRegisterClass *RC);
/external/ltp/testcases/network/stress/route/
H A Droute4-redirect207 RC=0
209 test_body || RC=`expr $RC + 1`
212 exit $RC

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