/external/mesa3d/src/gallium/auxiliary/gallivm/ |
H A D | lp_bld_debug.cpp | 295 MCInst Inst; local 305 if (!DisAsm->getInstruction(Inst, Size, memoryObject, 335 Printer->printInst(&Inst, Out, ""); 337 Printer->printInst(&Inst, Out); 339 Printer->printInst(&Inst); 350 const MCInstrDesc &TID = TII->get(Inst.getOpcode()); 352 const TargetInstrDesc &TID = TII->get(Inst.getOpcode()); 360 for (unsigned i = 0; i < Inst.getNumOperands(); ++i) { 361 const MCOperand &operand = Inst.getOperand(i);
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/external/swiftshader/third_party/LLVM/include/llvm/Analysis/ |
H A D | MemoryDependenceAnalysis.h | 105 static MemDepResult getDef(Instruction *Inst) { argument 106 assert(Inst && "Def requires inst"); 107 return MemDepResult(PairTy(Inst, Def)); 109 static MemDepResult getClobber(Instruction *Inst) { argument 110 assert(Inst && "Clobber requires inst"); 111 return MemDepResult(PairTy(Inst, Clobber)); 183 static MemDepResult getDirty(Instruction *Inst) { argument 184 return MemDepResult(PairTy(Inst, Invalid)); 435 void verifyRemoved(Instruction *Inst) const;
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
H A D | X86MCInstLower.cpp | 231 static void SimplifyShortImmForm(MCInst &Inst, unsigned Opcode) { argument 232 unsigned ImmOp = Inst.getNumOperands() - 1; 233 assert(Inst.getOperand(0).isReg() && Inst.getOperand(ImmOp).isImm() && 234 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() && 235 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) || 236 Inst.getNumOperands() == 2) && "Unexpected instruction!"); 239 unsigned Reg = Inst 251 SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, unsigned Opcode) argument [all...] |
/external/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCTargetDesc.cpp | 241 bool isUnconditionalBranch(const MCInst &Inst) const override { 243 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL) 245 return MCInstrAnalysis::isUnconditionalBranch(Inst); 248 bool isConditionalBranch(const MCInst &Inst) const override { 250 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL) 252 return MCInstrAnalysis::isConditionalBranch(Inst); 255 bool evaluateBranch(const MCInst &Inst, uint64_t Addr, 258 if (Info->get(Inst [all...] |
/external/llvm/lib/Transforms/Scalar/ |
H A D | LoopVersioningLICM.cpp | 382 for (auto &Inst : *Block) { 384 if (!instructionSafeForVersioning(&Inst)) 487 for (auto &Inst : *Block) { 489 if (!Inst.mayReadFromMemory() && !Inst.mayWriteToMemory()) 494 Inst.setMetadata( 496 MDNode::concatenate(Inst.getMetadata(LLVMContext::MD_noalias), 497 MDNode::get(Inst.getContext(), NoAliases))); 499 Inst.setMetadata( 501 MDNode::concatenate(Inst [all...] |
/external/llvm/lib/Target/AArch64/AsmParser/ |
H A D | AArch64AsmParser.cpp | 86 bool validateInstruction(MCInst &Inst, SmallVectorImpl<SMLoc> &Loc); 1149 void addExpr(MCInst &Inst, const MCExpr *Expr) const { argument 1152 Inst.addOperand(MCOperand::createImm(0)); 1154 Inst.addOperand(MCOperand::createImm(CE->getValue())); 1156 Inst.addOperand(MCOperand::createExpr(Expr)); 1159 void addRegOperands(MCInst &Inst, unsigned N) const { argument 1161 Inst.addOperand(MCOperand::createReg(getReg())); 1164 void addGPR32as64Operands(MCInst &Inst, unsigned N) const { argument 1173 Inst.addOperand(MCOperand::createReg(Reg)); 1176 void addVectorReg64Operands(MCInst &Inst, unsigne argument 1183 addVectorReg128Operands(MCInst &Inst, unsigned N) const argument 1190 addVectorRegLoOperands(MCInst &Inst, unsigned N) const argument 1196 addVectorList64Operands(MCInst &Inst, unsigned N) const argument 1209 addVectorList128Operands(MCInst &Inst, unsigned N) const argument 1221 addVectorIndex1Operands(MCInst &Inst, unsigned N) const argument 1226 addVectorIndexBOperands(MCInst &Inst, unsigned N) const argument 1231 addVectorIndexHOperands(MCInst &Inst, unsigned N) const argument 1236 addVectorIndexSOperands(MCInst &Inst, unsigned N) const argument 1241 addVectorIndexDOperands(MCInst &Inst, unsigned N) const argument 1246 addImmOperands(MCInst &Inst, unsigned N) const argument 1254 addAddSubImmOperands(MCInst &Inst, unsigned N) const argument 1265 addAddSubImmNegOperands(MCInst &Inst, unsigned N) const argument 1277 addCondCodeOperands(MCInst &Inst, unsigned N) const argument 1282 addAdrpLabelOperands(MCInst &Inst, unsigned N) const argument 1291 addAdrLabelOperands(MCInst &Inst, unsigned N) const argument 1296 addUImm12OffsetOperands(MCInst &Inst, unsigned N) const argument 1307 addSImm9Operands(MCInst &Inst, unsigned N) const argument 1313 addSImm7s4Operands(MCInst &Inst, unsigned N) const argument 1319 addSImm7s8Operands(MCInst &Inst, unsigned N) const argument 1325 addSImm7s16Operands(MCInst &Inst, unsigned N) const argument 1331 addImm0_1Operands(MCInst &Inst, unsigned N) const argument 1337 addImm0_7Operands(MCInst &Inst, unsigned N) const argument 1343 addImm1_8Operands(MCInst &Inst, unsigned N) const argument 1349 addImm0_15Operands(MCInst &Inst, unsigned N) const argument 1355 addImm1_16Operands(MCInst &Inst, unsigned N) const argument 1362 addImm0_31Operands(MCInst &Inst, unsigned N) const argument 1368 addImm1_31Operands(MCInst &Inst, unsigned N) const argument 1374 addImm1_32Operands(MCInst &Inst, unsigned N) const argument 1380 addImm0_63Operands(MCInst &Inst, unsigned N) const argument 1386 addImm1_63Operands(MCInst &Inst, unsigned N) const argument 1392 addImm1_64Operands(MCInst &Inst, unsigned N) const argument 1398 addImm0_127Operands(MCInst &Inst, unsigned N) const argument 1404 addImm0_255Operands(MCInst &Inst, unsigned N) const argument 1410 addImm0_65535Operands(MCInst &Inst, unsigned N) const argument 1416 addImm32_63Operands(MCInst &Inst, unsigned N) const argument 1422 addLogicalImm32Operands(MCInst &Inst, unsigned N) const argument 1430 addLogicalImm64Operands(MCInst &Inst, unsigned N) const argument 1437 addLogicalImm32NotOperands(MCInst &Inst, unsigned N) const argument 1445 addLogicalImm64NotOperands(MCInst &Inst, unsigned N) const argument 1453 addSIMDImmType10Operands(MCInst &Inst, unsigned N) const argument 1460 addBranchTarget26Operands(MCInst &Inst, unsigned N) const argument 1474 addPCRelLabel19Operands(MCInst &Inst, unsigned N) const argument 1488 addBranchTarget14Operands(MCInst &Inst, unsigned N) const argument 1502 addFPImmOperands(MCInst &Inst, unsigned N) const argument 1507 addBarrierOperands(MCInst &Inst, unsigned N) const argument 1512 addMRSSystemRegisterOperands(MCInst &Inst, unsigned N) const argument 1518 addMSRSystemRegisterOperands(MCInst &Inst, unsigned N) const argument 1524 addSystemPStateFieldWithImm0_1Operands(MCInst &Inst, unsigned N) const argument 1530 addSystemPStateFieldWithImm0_15Operands(MCInst &Inst, unsigned N) const argument 1536 addSysCROperands(MCInst &Inst, unsigned N) const argument 1541 addPrefetchOperands(MCInst &Inst, unsigned N) const argument 1546 addPSBHintOperands(MCInst &Inst, unsigned N) const argument 1551 addShifterOperands(MCInst &Inst, unsigned N) const argument 1558 addExtendOperands(MCInst &Inst, unsigned N) const argument 1566 addExtend64Operands(MCInst &Inst, unsigned N) const argument 1574 addMemExtendOperands(MCInst &Inst, unsigned N) const argument 1586 addMemExtend8Operands(MCInst &Inst, unsigned N) const argument 1595 addMOVZMovAliasOperands(MCInst &Inst, unsigned N) const argument 1604 addMOVNMovAliasOperands(MCInst &Inst, unsigned N) const argument 3437 validateInstruction(MCInst &Inst, SmallVectorImpl<SMLoc> &Loc) argument 4013 MCInst Inst; local 4359 MCInst Inst; local [all...] |
/external/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmInstrumentation.cpp | 184 void InstrumentAndEmitInstruction(const MCInst &Inst, 189 InstrumentMOVS(Inst, Operands, Ctx, MII, Out); 193 InstrumentMOV(Inst, Operands, Ctx, MII, Out); 195 RepPrefix = (Inst.getOpcode() == X86::REP_PREFIX); 197 EmitInstruction(Out, Inst); 228 void InstrumentMOVS(const MCInst &Inst, OperandVector &Operands, 230 void InstrumentMOV(const MCInst &Inst, OperandVector &Operands, 238 MCInst Inst; local 239 Inst.setOpcode(Size == 32 ? X86::LEA32r : X86::LEA64r); 240 Inst 347 InstrumentMOVS(const MCInst &Inst, OperandVector &Operands, MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out) argument 374 InstrumentMOV(const MCInst &Inst, OperandVector &Operands, MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out) argument 636 MCInst Inst; local 706 MCInst Inst; local 908 MCInst Inst; local 978 MCInst Inst; local 1032 InstrumentAndEmitInstruction( const MCInst &Inst, OperandVector &Operands, MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out) argument 1038 EmitInstruction(MCStreamer &Out, const MCInst &Inst) argument [all...] |
/external/llvm/lib/Analysis/ |
H A D | InstCount.cpp | 32 STATISTIC(Num ## OPCODE ## Inst, "Number of " #OPCODE " insts"); 45 void visit##OPCODE(CLASS &) { ++Num##OPCODE##Inst; ++TotalInsts; }
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsAsmBackend.h | 57 /// \param Inst - The instruction to test. 58 bool mayNeedRelaxation(const MCInst &Inst) const override { 75 /// \param Inst - The instruction to relax, which may be the same 78 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
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/external/llvm/lib/Target/SystemZ/AsmParser/ |
H A D | SystemZAsmParser.cpp | 120 void addExpr(MCInst &Inst, const MCExpr *Expr) const { argument 123 Inst.addOperand(MCOperand::createImm(0)); 125 Inst.addOperand(MCOperand::createImm(CE->getValue())); 127 Inst.addOperand(MCOperand::createExpr(Expr)); 253 void addBDVAddrOperands(MCInst &Inst, unsigned N) const { argument 256 Inst.addOperand(MCOperand::createReg(Mem.Base)); 257 addExpr(Inst, Mem.Disp); 258 Inst.addOperand(MCOperand::createReg(Mem.Index)); 268 void addRegOperands(MCInst &Inst, unsigned N) const { argument 270 Inst 272 addAccessRegOperands(MCInst &Inst, unsigned N) const argument 277 addImmOperands(MCInst &Inst, unsigned N) const argument 281 addBDAddrOperands(MCInst &Inst, unsigned N) const argument 287 addBDXAddrOperands(MCInst &Inst, unsigned N) const argument 294 addBDLAddrOperands(MCInst &Inst, unsigned N) const argument 301 addImmTLSOperands(MCInst &Inst, unsigned N) const argument 790 MCInst Inst; local [all...] |
/external/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
H A D | WebAssemblyAsmBackend.cpp | 56 bool mayNeedRelaxation(const MCInst &Inst) const override { return false; } 58 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
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/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
H A D | AMDGPUAsmBackend.cpp | 55 virtual void relaxInstruction(const MCInst &Inst, MCInst &Res) const { argument 58 virtual bool mayNeedRelaxation(const MCInst &Inst) const { return false; }
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/external/spirv-llvm/lib/SPIRV/libSPIRV/ |
H A D | SPIRVBasicBlock.h | 96 SPIRVInstructionVector::const_iterator find(const SPIRVInstruction *Inst) 98 return std::find(InstVec.begin(), InstVec.end(), Inst);
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/external/swiftshader/third_party/LLVM/include/llvm/MC/ |
H A D | MCAsmBackend.h | 104 /// \param Inst - The instruction to test. 105 virtual bool MayNeedRelaxation(const MCInst &Inst) const = 0; 110 /// \param Inst - The instruction to relax, which may be the same as the 113 virtual void RelaxInstruction(const MCInst &Inst, MCInst &Res) const = 0;
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/external/swiftshader/third_party/LLVM/lib/Analysis/ |
H A D | InstCount.cpp | 31 STATISTIC(Num ## OPCODE ## Inst, "Number of " #OPCODE " insts"); 44 void visit##OPCODE(CLASS &) { ++Num##OPCODE##Inst; ++TotalInsts; }
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsAsmBackend.cpp | 50 /// \param Inst - The instruction to test. 51 bool MayNeedRelaxation(const MCInst &Inst) const { 58 /// \param Inst - The instruction to relax, which may be the same as the 61 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const { argument
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/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/ |
H A D | X86AsmBackend.cpp | 108 bool MayNeedRelaxation(const MCInst &Inst) const; 110 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const; 217 bool X86AsmBackend::MayNeedRelaxation(const MCInst &Inst) const { 219 if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode()) 226 if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode()) 233 for (unsigned i = 0; i < Inst.getNumOperands(); ++i) { 234 const MCOperand &Op = Inst.getOperand(i); 249 void X86AsmBackend::RelaxInstruction(const MCInst &Inst, MCIns argument [all...] |
/external/abi-compliance-checker/ |
H A D | Makefile.pl | 259 my $Inst = $Path; 260 $Inst=~s/\A\Q$ARCHIVE_DIR\E/$To/; 263 mkpath($Inst); 267 mkpath(dirname($Inst)); 268 copy($Path, $Inst);
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/external/abi-dumper/ |
H A D | Makefile.pl | 228 my $Inst = $Path; 229 $Inst=~s/\A\Q$ARCHIVE_DIR\E/$To/; 232 mkpath($Inst); 236 mkpath(dirname($Inst)); 237 copy($Path, $Inst);
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/external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
H A D | R600MCCodeEmitter.cpp | 131 uint64_t Inst = getBinaryCodeForInstr(MI, Fixups, STI); local 135 uint64_t ISAOpCode = Inst & (0x3FFULL << 39); 136 Inst &= ~(0x3FFULL << 39); 137 Inst |= ISAOpCode << 1; 139 Emit(Inst, OS);
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/external/swiftshader/third_party/LLVM/lib/Transforms/Scalar/ |
H A D | DeadStoreElimination.cpp | 165 getLocForWrite(Instruction *Inst, AliasAnalysis &AA) { argument 166 if (StoreInst *SI = dyn_cast<StoreInst>(Inst)) 169 if (MemIntrinsic *MI = dyn_cast<MemIntrinsic>(Inst)) { 180 IntrinsicInst *II = dyn_cast<IntrinsicInst>(Inst); 204 getLocForRead(Instruction *Inst, AliasAnalysis &AA) { argument 205 assert(hasMemoryWrite(Inst) && "Unknown instruction case"); 209 if (MemTransferInst *MTI = dyn_cast<MemTransferInst>(Inst)) 376 /// isPossibleSelfRead - If 'Inst' might be a self read (i.e. a noop copy of a 389 static bool isPossibleSelfRead(Instruction *Inst, argument 394 AliasAnalysis::Location InstReadLoc = getLocForRead(Inst, A 428 Instruction *Inst = BBI++; local 500 << *DepWrite << "\\n KILLER: " << *Inst << '\\n'); local 628 Instruction *Inst = BBI++; local [all...] |
/external/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUOpenCLImageTypeLoweringPass.cpp | 154 auto Inst = dyn_cast<CallInst>(Use.getUser()); local 155 if (!Inst) { 159 Function *F = Inst->getCalledFunction(); 175 Inst->replaceAllUsesWith(Replacement); 176 InstsToErase.push_back(Inst); 187 auto Inst = dyn_cast<CallInst>(Use.getUser()); local 188 if (!Inst) { 192 Function *F = Inst->getCalledFunction(); 204 Inst->replaceAllUsesWith(Replacement); 205 InstsToErase.push_back(Inst); [all...] |
/external/swiftshader/third_party/LLVM/lib/AsmParser/ |
H A D | LLParser.cpp | 53 Instruction *Inst = I->first; local 62 Inst->setMetadata(MDList[i].MDKind, NumberedMetadata[SlotNo]); 1065 bool LLParser::ParseInstructionMetadata(Instruction *Inst, 1090 Inst->setMetadata(MDK, ID.MDNodeVal); 1097 Inst->setMetadata(MDK, Node); 1101 ForwardRefInstMetadata[Inst].push_back(R); 1786 LocTy NameLoc, Instruction *Inst) { 1788 if (Inst->getType()->isVoidTy()) { 1808 if (FI->second.first->getType() != Inst->getType()) 1811 FI->second.first->replaceAllUsesWith(Inst); [all...] |
/external/swiftshader/third_party/LLVM/lib/MC/ |
H A D | MCPureStreamer.cpp | 27 virtual void EmitInstToFragment(const MCInst &Inst); 28 virtual void EmitInstToData(const MCInst &Inst); 192 void MCPureStreamer::EmitInstToFragment(const MCInst &Inst) { argument 193 MCInstFragment *IF = new MCInstFragment(Inst, getCurrentSectionData()); 202 getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, Fixups); 209 void MCPureStreamer::EmitInstToData(const MCInst &Inst) { argument 215 getAssembler().getEmitter().EncodeInstruction(Inst, VecOS, Fixups);
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/external/llvm/include/llvm/Analysis/ |
H A D | MemoryDependenceAnalysis.h | 122 static MemDepResult getDef(Instruction *Inst) { argument 123 assert(Inst && "Def requires inst"); 124 return MemDepResult(ValueTy::create<Def>(Inst)); 126 static MemDepResult getClobber(Instruction *Inst) { argument 127 assert(Inst && "Clobber requires inst"); 128 return MemDepResult(ValueTy::create<Clobber>(Inst)); 193 static MemDepResult getDirty(Instruction *Inst) { argument 194 return MemDepResult(ValueTy::create<Invalid>(Inst)); 467 void verifyRemoved(Instruction *Inst) const;
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