/external/llvm/test/MC/ARM/ |
H A D | basic-thumb-instructions.s | 598 @ SUB (immediate) 610 @ SUB (SP minus immediate) 620 @ SUB (register)
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/external/pcre/dist2/src/sljit/ |
H A D | sljitNativeX86_64.c | 180 *inst++ = MOD_REG | SUB | 4; 212 *inst++ = MOD_REG | SUB | 4; 221 *inst++ = MOD_REG | SUB | 4;
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/external/swiftshader/third_party/LLVM/test/MC/ARM/ |
H A D | basic-thumb-instructions.s | 547 @ SUB (immediate) 559 @ SUB (SP minus immediate) 569 @ SUB (register)
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/external/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelDAGToDAG.cpp | 278 case ISD::SUB: { 669 } else if (Addr.getOpcode() == ISD::SUB) { 679 SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32, 736 } else if (Addr.getOpcode() == ISD::SUB) { 749 SDValue Sub = CurDAG->getNode(ISD::SUB, DL, MVT::i32,
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H A D | AMDGPUISelLowering.cpp | 376 setOperationAction(ISD::SUB, VT, Expand); 1317 Rem = DAG.getNode(ISD::SUB, DL, VT, LHS, Rem); 1402 SDValue REM_sub = DAG.getNode(ISD::SUB, DL, VT, REM, RHS); 1442 SDValue NEG_RCP_LO = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), 1457 SDValue RCP_S_E = DAG.getNode(ISD::SUB, DL, VT, RCP, E); 1470 SDValue Remainder = DAG.getNode(ISD::SUB, DL, VT, Num, Num_S_Remainder); 1494 SDValue Quotient_S_One = DAG.getNode(ISD::SUB, DL, VT, Quotient, 1508 SDValue Remainder_S_Den = DAG.getNode(ISD::SUB, DL, VT, Remainder, Den); 1577 Div = DAG.getNode(ISD::SUB, DL, VT, Div, DSign); 1578 Rem = DAG.getNode(ISD::SUB, D [all...] |
/external/llvm/lib/Target/Lanai/ |
H A D | LanaiISelLowering.cpp | 128 setTargetDAGCombine(ISD::SUB); 953 Res = DAG.getNode(ISD::SUB, DL, VT, Res, Op); 1032 SDValue Sub = DAG.getNode(ISD::SUB, DL, MVT::i32, StackPointer, Size); 1260 ISD::SUB, dl, MVT::i32, DAG.getConstant(VTBits, dl, MVT::i32), ShAmt); 1410 // PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB. 1435 case ISD::SUB:
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/external/llvm/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 336 User->getOpcode() == X86ISD::SUB || 337 User->getOpcode() == ISD::SUB) { 414 case X86ISD::SUB: 1276 case ISD::SUB: { 1333 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS); 2499 case X86ISD::SUB: { 2500 // Sometimes a SUB is used to perform comparison. 2501 if (Opcode == X86ISD::SUB && Node->hasAnyUseOfValue(0)) 2549 // Replace SUB|CMP with TEST, since SUB ha [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeIntegerTypes.cpp | 123 case ISD::SUB: 382 ISD::SUB, dl, NVT, Op, 551 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB; 744 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB; 1385 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break; 1614 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode); 1615 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt); 1769 RevOpc = ISD::SUB; 1775 Hi = DAG.getNode(ISD::SUB, dl, NVT, makeArrayRef(HiOps, 2)); 1806 Lo = DAG.getNode(ISD::SUB, d [all...] |
H A D | DAGCombiner.cpp | 1355 case ISD::SUB: return visitSUB(N); 1472 case ISD::SUB: 1668 if (N0.getOpcode() == ISD::SUB) 1671 return DAG.getNode(ISD::SUB, DL, VT, 1681 if (N0.getOpcode() == ISD::SUB && isNullConstant(N0.getOperand(0))) 1682 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1, N0.getOperand(1)); 1684 if (N1.getOpcode() == ISD::SUB && isNullConstant(N1.getOperand(0))) 1685 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1.getOperand(1)); 1687 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1690 if (N0.getOpcode() == ISD::SUB [all...] |
H A D | TargetLowering.cpp | 1136 case ISD::SUB: { 1413 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp, 2008 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2056 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 2085 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2100 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2111 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2871 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 2950 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q); 3113 SDValue Exponent = DAG.getNode(ISD::SUB, d [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 604 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB && 628 if (N.getOpcode() == ISD::SUB) 677 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB && 691 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add; 717 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift && 788 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB && 810 if (N.getOpcode() != ISD::SUB) { 845 ARM_AM::AddrOpc AddSub = N.getOpcode() != ISD::SUB ? ARM_AM::add:ARM_AM::sub; 871 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift && 983 if (N.getOpcode() == ISD::SUB) { [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
H A D | SPUISelLowering.cpp | 280 setOperationAction(ISD::SUB, MVT::i8, Custom); 281 setOperationAction(ISD::SUB, MVT::i64, Legal); 410 setOperationAction(ISD::SUB, VT, Legal); 707 DAG.getNode(ISD::SUB, dl, MVT::i32, 909 SDValue offset_compl = DAG.getNode(ISD::SUB, dl, MVT::i32, 913 SDValue surplus = DAG.getNode(ISD::SUB, dl, MVT::i32, 2215 case ISD::SUB: { 2574 SDValue lhsSignMag2TC = DAG.getNode(ISD::SUB, dl, IntVT, signMag2TC, i64lhs); 2581 SDValue rhsSignMag2TC = DAG.getNode(ISD::SUB, dl, IntVT, signMag2TC, i64rhs); 2808 case ISD::SUB [all...] |
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeIntegerTypes.cpp | 105 case ISD::SUB: 317 return DAG.getNode(ISD::SUB, dl, NVT, Op, 457 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB; 620 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB; 1140 case ISD::SUB: ExpandIntRes_ADDSUB(N, Lo, Hi); break; 1399 SDValue Amt2 = DAG.getNode(ISD::SUB, ShTy, 1438 SDValue AmtExcess = DAG.getNode(ISD::SUB, dl, ShTy, Amt, NVBitsNode); 1439 SDValue AmtLack = DAG.getNode(ISD::SUB, dl, ShTy, NVBitsNode, Amt); 1550 Lo = DAG.getNode(ISD::SUB, dl, NVT, LoOps, 2); 1551 Hi = DAG.getNode(ISD::SUB, d [all...] |
H A D | LegalizeVectorOps.cpp | 140 case ISD::SUB:
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H A D | TargetLowering.cpp | 1809 case ISD::SUB: { 1969 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp, 2412 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2456 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { 2476 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2488 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2499 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 3278 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0)); 3351 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 100 setOperationAction(ISD::SUB, MVT::i64, Custom); 217 case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG); 241 case ISD::SUB: 721 (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && 1701 SDValue Result = DAG.getNode(ISD::SUB, dl, VT, 1717 SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2);
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/external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 99 setOperationAction(ISD::SUB, MVT::i64, Custom); 183 case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG); 203 case ISD::SUB: 708 (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && 1383 SDValue Result = DAG.getNode(ISD::SUB, dl, VT, 1399 SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2);
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelDAGToDAG.cpp | 428 case ISD::SUB:
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZSelectionDAGInfo.cpp | 260 SDValue Len = DAG.getNode(ISD::SUB, DL, PtrVT, End, Src);
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/external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
H A D | AlphaISelLowering.cpp | 557 SDValue FPDataPtr = DAG.getNode(ISD::SUB, dl, MVT::i64, DataPtr, 594 SDValue bm = DAG.getNode(ISD::SUB, dl, MVT::i64, 600 SDValue ShAmt_Neg = DAG.getNode(ISD::SUB, dl, MVT::i64, 687 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Op.getOperand(0), Tmp1);
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/external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
H A D | MSP430ISelDAGToDAG.cpp | 431 case ISD::SUB:
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/external/v8/src/arm/ |
H A D | constants-arm.h | 143 SUB = 2 << 21, // Subtract. enumerator in enum:v8::internal::Opcode
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/external/v8/src/arm64/ |
H A D | macro-assembler-arm64-inl.h | 157 AddSubMacro(rd, rn, -operand.ImmediateValue(), LeaveFlags, SUB); 169 AddSubMacro(rd, rn, -operand.ImmediateValue(), SetFlags, SUB); 184 AddSubMacro(rd, rn, operand, LeaveFlags, SUB); 197 AddSubMacro(rd, rn, operand, SetFlags, SUB);
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/external/jarjar/lib/ |
H A D | asm-commons-4.0.jar | META-INF/MANIFEST.MF org/objectweb/asm/commons/AdviceAdapter.class " package org.objectweb.asm ... |
/external/owasp/sanitizer/tools/findbugs/lib/ |
H A D | asm-commons-3.3.jar | META-INF/MANIFEST.MF org/objectweb/asm/commons/AdviceAdapter.class " package org.objectweb.asm ... |