Searched refs:reg (Results 126 - 150 of 1101) sorted by relevance

1234567891011>>

/external/libunwind/src/sh/
H A DGresume.c126 int reg; local
130 for (reg = 0; reg <= UNW_REG_LAST; ++reg)
132 Debug (16, "copying %s %d\n", unw_regname (reg), reg);
133 if (unw_is_fpreg (reg))
135 if (tdep_access_fpreg (c, reg, &fpval, 0) >= 0)
136 as->acc.access_fpreg (as, reg, &fpval, 1, arg);
140 if (tdep_access_reg (c, reg,
[all...]
/external/mesa3d/src/gallium/drivers/nv50/codegen/
H A Dnv50_ir_build_util.cpp57 unsigned int pos = u32Hash(imm->reg.data.u32);
185 Instruction *insn = new_Instruction(func, OP_MOV, typeOfSize(src->reg.size));
188 insn->getDef(0)->reg.data.id = id;
198 Instruction *insn = new_Instruction(func, OP_MOV, typeOfSize(dst->reg.size));
202 insn->getSrc(0)->reg.data.id = id;
228 insn->setType((dst->reg.file == FILE_PREDICATE ||
229 dst->reg.file == FILE_FLAGS) ? TYPE_U8 : ty, ty);
237 if (dst->reg.file == FILE_FLAGS)
278 return mkOp2(OP_UNION, typeOfSize(dst->reg.size), dst, def0, def1);
288 if (val->reg
339 LValue *reg = new_LValue(func, f); local
345 LValue *reg = new_LValue(func, f); local
[all...]
H A Dnv50_ir_print.cpp325 int idx = join->reg.data.id >= 0 ? join->reg.data.id : id;
326 char p = join->reg.data.id >= 0 ? '$' : '%';
330 switch (reg.file) {
333 if (reg.size == 2) {
341 if (reg.size == 8) {
344 if (reg.size == 16) {
347 if (reg.size == 12) {
353 if (reg.size == 2)
356 if (reg
[all...]
/external/valgrind/none/tests/x86/
H A Dbt_everything.c159 UInt reg; local
196 reg = 0;
203 case 0: c = btsl_reg(reg, bitoff, &reg); break;
204 case 1: c = btrl_reg(reg, bitoff, &reg); break;
205 case 2: c = btcl_reg(reg, bitoff, &reg); break;
206 case 3: c = btl_reg(reg, bitoff, &reg); brea
[all...]
/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DRegAllocLinearScan.cpp187 void recordRecentlyUsed(unsigned reg) { argument
188 assert(reg != 0 && "Recently used register is NOREG!");
190 *RecentNext++ = reg;
230 bool isRecentlyUsed(unsigned reg) const {
231 return reg == avoidWAW_ ||
232 std::find(RecentRegs.begin(), RecentRegs.end(), reg) != RecentRegs.end();
266 unsigned reg, float weight,
378 unsigned reg = i->first->reg;
379 if (TargetRegisterInfo::isVirtualRegister(reg))
625 unsigned reg = IP.first->reg; local
691 unsigned reg = Interval->reg; local
737 unsigned reg = Interval->reg; local
771 updateSpillWeights(std::vector<float> &Weights, unsigned reg, float weight, const TargetRegisterClass *RC) argument
1089 unsigned reg = I->reg; local
1144 unsigned reg = i->first->reg; local
1162 unsigned reg = Order[i]; local
1173 unsigned reg = Order[i]; local
1508 unsigned reg = i->first->reg; local
[all...]
H A DCalcSpillWeights.cpp52 if (TargetRegisterInfo::isVirtualRegister(li.reg))
58 // Return the preferred allocation register for reg, given a COPY instruction.
59 static unsigned copyHint(const MachineInstr *mi, unsigned reg, argument
63 if (mi->getOperand(0).getReg() == reg) {
79 const TargetRegisterClass *rc = mri.getRegClass(reg);
85 // reg:sub should match the physreg hreg.
104 bool noHint = mri.getRegAllocationHint(li.reg).first != 0;
109 for (MachineRegisterInfo::reg_iterator I = mri.reg_begin(li.reg);
128 tie(reads, writes) = mi->readsWritesVirtualRegister(li.reg);
141 unsigned hint = copyHint(mi, li.reg, tr
[all...]
/external/mesa3d/src/gallium/drivers/radeonsi/
H A Dradeonsi_pm4.c56 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val) argument
60 if (reg >= SI_CONFIG_REG_OFFSET && reg <= SI_CONFIG_REG_END) {
62 reg -= SI_CONFIG_REG_OFFSET;
64 } else if (reg >= SI_SH_REG_OFFSET && reg <= SI_SH_REG_END) {
66 reg -= SI_SH_REG_OFFSET;
68 } else if (reg >= SI_CONTEXT_REG_OFFSET && reg <= SI_CONTEXT_REG_END) {
70 reg
109 si_pm4_sh_data_end(struct si_pm4_state *state, unsigned reg) argument
[all...]
/external/mesa3d/src/gallium/auxiliary/tgsi/
H A Dtgsi_ureg.h850 ureg_negate( struct ureg_src reg )
852 assert(reg.File != TGSI_FILE_NULL);
853 reg.Negate ^= 1;
854 return reg;
858 ureg_abs( struct ureg_src reg )
860 assert(reg.File != TGSI_FILE_NULL);
861 reg.Absolute = 1;
862 reg.Negate = 0;
863 return reg;
867 ureg_swizzle( struct ureg_src reg, argument
889 ureg_scalar( struct ureg_src reg, int x ) argument
895 ureg_writemask( struct ureg_dst reg, unsigned writemask ) argument
912 ureg_predicate(struct ureg_dst reg, boolean negate, unsigned swizzle_x, unsigned swizzle_y, unsigned swizzle_z, unsigned swizzle_w) argument
930 ureg_dst_indirect( struct ureg_dst reg, struct ureg_src addr ) argument
941 ureg_src_indirect( struct ureg_src reg, struct ureg_src addr ) argument
953 ureg_src_dimension( struct ureg_src reg, int index ) argument
964 ureg_src_dimension_indirect( struct ureg_src reg, struct ureg_src addr, int index ) argument
[all...]
/external/mesa3d/src/mesa/drivers/dri/i965/
H A Dbrw_clip_unfilled.c53 struct brw_reg e = c->reg.tmp0;
54 struct brw_reg f = c->reg.tmp1;
57 struct brw_reg v0 = byte_offset(c->reg.vertex[0], hpos_offset);
58 struct brw_reg v1 = byte_offset(c->reg.vertex[1], hpos_offset);
59 struct brw_reg v2 = byte_offset(c->reg.vertex[2], hpos_offset);
94 brw_MUL(p, c->reg.dir, c->reg.dir, vec4(e));
114 get_element(c->reg.dir, 2),
151 get_element(c->reg.dir, 2),
162 byte_offset(c->reg
[all...]
/external/kernel-headers/original/uapi/asm-x86/asm/
H A Dmtrr.h91 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
92 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
/external/valgrind/VEX/priv/
H A Dhost_generic_regs.c107 HReg reg = univ->regs[i]; local
108 vassert(!hregIsInvalid(reg));
109 vassert(!hregIsVirtual(reg));
110 vassert(hregIndex(reg) == i);
113 HReg reg = univ->regs[i]; local
114 vassert(hregIsInvalid(reg));
120 /*--- Helpers for recording reg usage (for reg-alloc) ---*/
162 create duplicate entries -- each reg is only mentioned once.
164 void addHRegUse ( HRegUsage* tab, HRegMode mode, HReg reg )
[all...]
/external/llvm/lib/Target/BPF/
H A DBPFRegisterInfo.cpp68 unsigned reg = MI.getOperand(i - 1).getReg(); local
69 BuildMI(MBB, ++II, DL, TII.get(BPF::ADD_ri), reg)
70 .addReg(reg)
85 unsigned reg = MI.getOperand(i - 1).getReg(); local
87 BuildMI(MBB, ++II, DL, TII.get(BPF::MOV_rr), reg)
89 BuildMI(MBB, II, DL, TII.get(BPF::ADD_ri), reg)
90 .addReg(reg)
/external/llvm/lib/Target/Sparc/
H A DSparcFrameLowering.cpp291 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg)
292 if (!MRI->reg_nodbg_empty(reg))
295 for (unsigned reg = SP::L0; reg <= SP::L7; ++reg)
296 if (!MRI->reg_nodbg_empty(reg))
317 for (unsigned reg = SP::I0; reg <
[all...]
/external/clang/test/CodeGen/
H A Dbuiltins-systemz.c12 void test_htm1(struct __htm_tdb *tdb, int reg, int *mem, uint64_t *mem64) { argument
66 __builtin_tabort (reg);
80 __builtin_non_tx_store (mem64, (uint64_t)reg);
90 __builtin_non_tx_store (&g, reg);
101 __builtin_tx_assist (reg);
/external/syslinux/gpxe/src/drivers/net/
H A Dprism2.c175 static inline UINT16 hfa384x_getreg( hfa384x_t *hw, UINT reg )
178 return inw ( hw->iobase + reg );
180 return readw ( hw->membase + reg );
185 static inline void hfa384x_setreg( hfa384x_t *hw, UINT16 val, UINT reg )
188 outw ( val, hw->iobase + reg );
190 writew ( val, hw->membase + reg );
199 static inline UINT16 hfa384x_getreg_noswap( hfa384x_t *hw, UINT reg )
201 return hfa384x_getreg ( hw, reg );
203 static inline void hfa384x_setreg_noswap( hfa384x_t *hw, UINT16 val, UINT reg )
205 hfa384x_setreg ( hw, val, reg );
232 UINT16 reg = 0; local
295 UINT16 reg; local
342 UINT16 reg = 0; local
581 UINT16 reg; local
603 UINT16 reg; local
[all...]
/external/mesa3d/src/gallium/drivers/r300/compiler/
H A Dr300_fragprog_swizzle.c107 static int r300_swizzle_is_native(rc_opcode opcode, struct rc_src_register reg) argument
117 if (reg.Abs || reg.Negate)
121 unsigned int swz = GET_SWZ(reg.Swizzle, j);
134 if (GET_SWZ(reg.Swizzle, j) != RC_SWIZZLE_UNUSED)
137 if ((reg.Negate & relevant) && ((reg.Negate & relevant) != relevant))
140 sd = lookup_native_swizzle(reg.Swizzle);
141 if (!sd || (reg.File == RC_FILE_PRESUB && sd->srcp_stride == 0))
/external/syslinux/com32/elflink/ldlinux/
H A Dchainboot.c47 com32sys_t reg; local
61 reg.eax.l = max;
62 reg.ebx.l = 0;
63 reg.edx.w[0] = 0;
64 reg.edi.l = (uint32_t)buf;
65 reg.ebp.l = -1; /* XXX: limit? */
66 reg.esi.w[0] = rv;
68 pm_load_high(&reg);
70 size = reg.edi.l - (unsigned long)buf;
/external/libunwind/src/x86/
H A DGinit.c50 tdep_uc_addr (ucontext_t *uc, int reg) argument
52 return x86_r_uc_addr (uc, reg);
190 access_reg (unw_addr_space_t as, unw_regnum_t reg, unw_word_t *val, int write, argument
196 if (unw_is_fpreg (reg))
199 if (!(addr = x86_r_uc_addr (uc, reg)))
205 Debug (12, "%s <- %x\n", unw_regname (reg), *val);
210 Debug (12, "%s -> %x\n", unw_regname (reg), *val);
215 Debug (1, "bad register number %u\n", reg);
220 access_fpreg (unw_addr_space_t as, unw_regnum_t reg, unw_fpreg_t *val, argument
226 if (!unw_is_fpreg (reg))
[all...]
/external/mesa3d/src/gallium/drivers/radeon/
H A DR600RegisterInfo.cpp69 unsigned R600RegisterInfo::getHWRegIndex(unsigned reg) const
71 switch(reg) {
84 default: return getHWRegIndexGen(reg);
88 unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const
90 switch(reg) {
103 default: return getHWRegChanGen(reg);
/external/aac/libMpegTPDec/src/
H A Dtpdec_drm.cpp124 int reg /*!< crc region */
129 FDKcrcEndReg(&pDrm->crcInfo, hBs, reg);
/external/clang/test/Index/
H A Dannotate-tokens.c67 r_t reg; local
68 reg.field = 1;
239 // CHECK-RANGE2: Identifier: "reg" [68:3 - 68:6] DeclRefExpr=reg:67:7
/external/eclipse-basebuilder/basebuilder-3.6.2/org.eclipse.releng.basebuilder/plugins/org.apache.ant_1.7.1.v20090120-1145/lib/
H A Dant-apache-regexp.jar ... ant.BuildException org.apache.regexp.RE reg org.apache.regexp.RESyntaxException e int options
/external/llvm/include/llvm/CodeGen/
H A DLiveVariables.h212 bool removeVirtualRegisterKilled(unsigned reg, MachineInstr &MI) { argument
213 if (!getVarInfo(reg).removeKill(MI))
219 if (MO.isReg() && MO.isKill() && MO.getReg() == reg) {
248 bool removeVirtualRegisterDead(unsigned reg, MachineInstr &MI) { argument
249 if (!getVarInfo(reg).removeKill(MI))
255 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
281 void HandleVirtRegDef(unsigned reg, MachineInstr &MI);
282 void HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB, MachineInstr &MI);
/external/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegColoring.cpp30 #define DEBUG_TYPE "wasm-reg-coloring"
120 if (MRI->isLiveIn(LHS->reg) != MRI->isLiveIn(RHS->reg))
121 return MRI->isLiveIn(LHS->reg);
137 unsigned Old = LI->reg;
145 if (MRI->getRegClass(SortedIntervals[C]->reg) != RC)
155 unsigned New = SortedIntervals[Color]->reg;
161 << TargetRegisterInfo::virtReg2Index(LI->reg) << " to vreg"
169 unsigned Old = SortedIntervals[i]->reg;
/external/llvm/test/MC/AsmParser/
H A Dat-pseudo-variable.s28 .irp reg,%eax,%ebx
29 sub $2\@, \reg
45 .irp reg,%eax,%ebx
46 sub $4, \reg

Completed in 1834 milliseconds

1234567891011>>