Searched refs:cond (Results 1 - 25 of 55) sorted by relevance

123

/art/test/549-checker-types-merge/src/
H A DMain.java44 private Object testMergeNullContant(boolean cond) { argument
45 return cond ? null : new Main();
51 private Object testMergeClasses(boolean cond, ClassExtendsA a, ClassExtendsB b) { argument
53 return cond ? a : b;
59 private Object testMergeClasses(boolean cond, ClassExtendsA a, ClassSuper b) { argument
61 return cond ? a : b;
67 private Object testMergeClasses(boolean cond, ClassSuper a, ClassSuper b) { argument
69 return cond ? a : b;
75 private Object testMergeClasses(boolean cond, ClassOtherSuper a, ClassSuper b) { argument
77 return cond
83 testMergeClassWithInterface(boolean cond, ClassImplementsInterfaceA a, InterfaceSuper b) argument
91 testMergeClassWithInterface(boolean cond, ClassSuper a, InterfaceSuper b) argument
99 testMergeInterfaces(boolean cond, InterfaceExtendsA a, InterfaceSuper b) argument
107 testMergeInterfaces(boolean cond, InterfaceSuper a, InterfaceSuper b) argument
115 testMergeInterfaces(boolean cond, InterfaceExtendsA a, InterfaceExtendsB b) argument
123 testMergeInterfaces(boolean cond, InterfaceSuper a, InterfaceOtherSuper b) argument
[all...]
/art/test/557-checker-ref-equivalent/src/
H A DMain.java21 private void testRedundantPhiCycle(boolean cond) { argument
24 if (cond) {
33 private void testLoopPhisWithNullAndCrossUses(boolean cond) { argument
37 if (cond) {
/art/test/540-checker-rtp-bug/src/
H A DMain.java37 public static Final testKeepCheckCast(Object o, boolean cond) { argument
39 while (cond) {
41 cond = false;
55 public static void testKeepInstanceOf(Object o, boolean cond) { argument
57 while (cond) {
59 cond = false;
79 public static String testNoInline(Object o, boolean cond) { argument
81 while (cond) {
83 cond = false;
/art/compiler/utils/arm/
H A Dassembler_arm.h410 Condition cond = AL, SetCc set_cc = kCcDontCare) = 0;
412 virtual void ands(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) {
413 and_(rd, rn, so, cond, kCcSet);
417 Condition cond = AL, SetCc set_cc = kCcDontCare) = 0;
419 virtual void eors(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) {
420 eor(rd, rn, so, cond, kCcSet);
424 Condition cond = AL, SetCc set_cc = kCcDontCare) = 0;
426 virtual void subs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) {
427 sub(rd, rn, so, cond, kCcSet);
431 Condition cond
[all...]
H A Dassembler_thumb2.h73 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
76 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
79 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
82 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
85 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
88 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
91 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
94 Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
96 void tst(Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
98 void teq(Register rn, const ShifterOperand& so, Condition cond
489 CompareAndBranch(uint32_t location, Register rn, Condition cond) argument
629 Fixup(Register rn, Register rt2, SRegister sd, DRegister dd, Condition cond, Type type, Size size, uint32_t location) argument
824 CheckCondition(Condition cond) argument
836 CheckConditionLastIt(Condition cond) argument
[all...]
H A Dassembler_thumb2.cc325 inline int16_t Thumb2Assembler::BEncoding16(int32_t offset, Condition cond) { argument
328 if (cond != AL) {
330 encoding |= B12 | (static_cast<int32_t>(cond) << 8) | ((offset >> 1) & 0xff);
338 inline int32_t Thumb2Assembler::BEncoding32(int32_t offset, Condition cond) { argument
344 if (cond != AL) {
346 // Encode cond, move imm6 from bits 12-17 to bits 16-21 and move J1 and J2.
347 encoding |= (static_cast<int32_t>(cond) << 22) | ((offset & 0x3f000) << (16 - 12)) |
361 inline int16_t Thumb2Assembler::CbxzEncoding16(Register rn, int32_t offset, Condition cond) { argument
365 DCHECK(cond == EQ || cond
542 and_(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
548 eor(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
554 sub(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
560 rsb(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
566 add(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
572 adc(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
578 sbc(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
584 rsc(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
590 tst(Register rn, const ShifterOperand& so, Condition cond) argument
596 teq(Register rn, const ShifterOperand& so, Condition cond) argument
602 cmp(Register rn, const ShifterOperand& so, Condition cond) argument
607 cmn(Register rn, const ShifterOperand& so, Condition cond) argument
612 orr(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
618 orn(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
624 mov(Register rd, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
630 bic(Register rd, Register rn, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
636 mvn(Register rd, const ShifterOperand& so, Condition cond, SetCc set_cc) argument
642 mul(Register rd, Register rn, Register rm, Condition cond) argument
667 mla(Register rd, Register rn, Register rm, Register ra, Condition cond) argument
685 mls(Register rd, Register rn, Register rm, Register ra, Condition cond) argument
703 smull(Register rd_lo, Register rd_hi, Register rn, Register rm, Condition cond) argument
721 umull(Register rd_lo, Register rd_hi, Register rn, Register rm, Condition cond) argument
739 sdiv(Register rd, Register rn, Register rm, Condition cond) argument
756 udiv(Register rd, Register rn, Register rm, Condition cond) argument
773 sbfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond) argument
794 ubfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond) argument
815 ldr(Register rd, const Address& ad, Condition cond) argument
820 str(Register rd, const Address& ad, Condition cond) argument
825 ldrb(Register rd, const Address& ad, Condition cond) argument
830 strb(Register rd, const Address& ad, Condition cond) argument
835 ldrh(Register rd, const Address& ad, Condition cond) argument
840 strh(Register rd, const Address& ad, Condition cond) argument
845 ldrsb(Register rd, const Address& ad, Condition cond) argument
850 ldrsh(Register rd, const Address& ad, Condition cond) argument
855 ldrd(Register rd, const Address& ad, Condition cond) argument
860 ldrd(Register rd, Register rd2, const Address& ad, Condition cond) argument
872 strd(Register rd, const Address& ad, Condition cond) argument
877 strd(Register rd, Register rd2, const Address& ad, Condition cond) argument
889 ldm(BlockAddressMode am, Register base, RegList regs, Condition cond) argument
900 ldr(static_cast<Register>(reg), Address(base, kRegisterSize, Address::PostIndex), cond); local
907 stm(BlockAddressMode am, Register base, RegList regs, Condition cond) argument
919 str(static_cast<Register>(reg), Address(base, -kRegisterSize, strmode), cond); local
926 vmovs(SRegister sd, float s_imm, Condition cond) argument
941 vmovd(DRegister dd, double d_imm, Condition cond) argument
956 vmovs(SRegister sd, SRegister sm, Condition cond) argument
961 vmovd(DRegister dd, DRegister dm, Condition cond) argument
966 vadds(SRegister sd, SRegister sn, SRegister sm, Condition cond) argument
972 vaddd(DRegister dd, DRegister dn, DRegister dm, Condition cond) argument
978 vsubs(SRegister sd, SRegister sn, SRegister sm, Condition cond) argument
984 vsubd(DRegister dd, DRegister dn, DRegister dm, Condition cond) argument
990 vmuls(SRegister sd, SRegister sn, SRegister sm, Condition cond) argument
996 vmuld(DRegister dd, DRegister dn, DRegister dm, Condition cond) argument
1002 vmlas(SRegister sd, SRegister sn, SRegister sm, Condition cond) argument
1008 vmlad(DRegister dd, DRegister dn, DRegister dm, Condition cond) argument
1014 vmlss(SRegister sd, SRegister sn, SRegister sm, Condition cond) argument
1020 vmlsd(DRegister dd, DRegister dn, DRegister dm, Condition cond) argument
1026 vdivs(SRegister sd, SRegister sn, SRegister sm, Condition cond) argument
1032 vdivd(DRegister dd, DRegister dn, DRegister dm, Condition cond) argument
1038 vabss(SRegister sd, SRegister sm, Condition cond) argument
1043 vabsd(DRegister dd, DRegister dm, Condition cond) argument
1048 vnegs(SRegister sd, SRegister sm, Condition cond) argument
1053 vnegd(DRegister dd, DRegister dm, Condition cond) argument
1058 vsqrts(SRegister sd, SRegister sm, Condition cond) argument
1062 vsqrtd(DRegister dd, DRegister dm, Condition cond) argument
1067 vcvtsd(SRegister sd, DRegister dm, Condition cond) argument
1072 vcvtds(DRegister dd, SRegister sm, Condition cond) argument
1077 vcvtis(SRegister sd, SRegister sm, Condition cond) argument
1082 vcvtid(SRegister sd, DRegister dm, Condition cond) argument
1087 vcvtsi(SRegister sd, SRegister sm, Condition cond) argument
1092 vcvtdi(DRegister dd, SRegister sm, Condition cond) argument
1097 vcvtus(SRegister sd, SRegister sm, Condition cond) argument
1102 vcvtud(SRegister sd, DRegister dm, Condition cond) argument
1107 vcvtsu(SRegister sd, SRegister sm, Condition cond) argument
1112 vcvtdu(DRegister dd, SRegister sm, Condition cond) argument
1117 vcmps(SRegister sd, SRegister sm, Condition cond) argument
1122 vcmpd(DRegister dd, DRegister dm, Condition cond) argument
1127 vcmpsz(SRegister sd, Condition cond) argument
1132 vcmpdz(DRegister dd, Condition cond) argument
1136 b(Label* label, Condition cond) argument
1142 bl(Label* label, Condition cond) argument
1175 Is32BitDataProcessing(Condition cond, Opcode opcode, SetCc set_cc, Register rn, Register rd, const ShifterOperand& so) argument
1425 Emit16BitDataProcessing(Condition cond, Opcode opcode, SetCc set_cc, Register rn, Register rd, const ShifterOperand& so) argument
1616 Emit16BitAddSub(Condition cond, Opcode opcode, SetCc set_cc, Register rn, Register rd, const ShifterOperand& so) argument
1776 EmitDataProcessing(Condition cond, Opcode opcode, SetCc set_cc, Register rn, Register rd, const ShifterOperand& so) argument
1792 EmitShift(Register rd, Register rm, Shift shift, uint8_t amount, Condition cond, SetCc set_cc) argument
1837 EmitShift(Register rd, Register rn, Shift shift, Register rm, Condition cond, SetCc set_cc) argument
2352 EmitLoadStore(Condition cond, bool load, bool byte, bool half, bool is_signed, Register rd, const Address& ad) argument
2499 EmitMultiMemOp(Condition cond, BlockAddressMode bam, bool load, Register base, RegList regs) argument
2568 EmitBranch(Condition cond, Label* label, bool link, bool x) argument
2637 clz(Register rd, Register rm, Condition cond) argument
2651 movw(Register rd, uint16_t imm16, Condition cond) argument
2669 movt(Register rd, uint16_t imm16, Condition cond) argument
2687 rbit(Register rd, Register rm, Condition cond) argument
2729 rev(Register rd, Register rm, Condition cond) argument
2735 rev16(Register rd, Register rm, Condition cond) argument
2741 revsh(Register rd, Register rm, Condition cond) argument
2747 ldrex(Register rt, Register rn, uint16_t imm, Condition cond) argument
2762 ldrex(Register rt, Register rn, Condition cond) argument
2767 strex(Register rd, Register rt, Register rn, uint16_t imm, Condition cond) argument
2787 ldrexd(Register rt, Register rt2, Register rn, Condition cond) argument
2803 strex(Register rd, Register rt, Register rn, Condition cond) argument
2811 strexd(Register rd, Register rt, Register rt2, Register rn, Condition cond) argument
2831 clrex(Condition cond) argument
2844 nop(Condition cond) argument
2852 vmovsr(SRegister sn, Register rt, Condition cond) argument
2867 vmovrs(Register rt, SRegister sn, Condition cond) argument
2882 vmovsrr(SRegister sm, Register rt, Register rt2, Condition cond) argument
2903 vmovrrs(Register rt, Register rt2, SRegister sm, Condition cond) argument
2925 vmovdrr(DRegister dm, Register rt, Register rt2, Condition cond) argument
2945 vmovrrd(Register rt, Register rt2, DRegister dm, Condition cond) argument
2966 vldrs(SRegister sd, const Address& ad, Condition cond) argument
2979 vstrs(SRegister sd, const Address& ad, Condition cond) argument
2993 vldrd(DRegister dd, const Address& ad, Condition cond) argument
3006 vstrd(DRegister dd, const Address& ad, Condition cond) argument
3020 vpushs(SRegister reg, int nregs, Condition cond) argument
3021 EmitVPushPop(static_cast<uint32_t>(reg), nregs, true, false, cond); local
3025 vpushd(DRegister reg, int nregs, Condition cond) argument
3026 EmitVPushPop(static_cast<uint32_t>(reg), nregs, true, true, cond); local
3030 vpops(SRegister reg, int nregs, Condition cond) argument
3031 EmitVPushPop(static_cast<uint32_t>(reg), nregs, false, false, cond); local
3035 vpopd(DRegister reg, int nregs, Condition cond) argument
3036 EmitVPushPop(static_cast<uint32_t>(reg), nregs, false, true, cond); local
3040 vldmiad(Register base_reg, DRegister reg, int nregs, Condition cond) argument
3052 vstmiad(Register base_reg, DRegister reg, int nregs, Condition cond) argument
3064 EmitVPushPop(uint32_t reg, int nregs, bool push, bool dbl, Condition cond) argument
3070 EmitVLdmOrStm(int32_t rest, uint32_t reg, int nregs, Register rn, bool is_load, bool dbl, Condition cond) argument
3109 EmitVFPsss(Condition cond, int32_t opcode, SRegister sd, SRegister sn, SRegister sm) argument
3127 EmitVFPddd(Condition cond, int32_t opcode, DRegister dd, DRegister dn, DRegister dm) argument
3145 EmitVFPsd(Condition cond, int32_t opcode, SRegister sd, DRegister dm) argument
3160 EmitVFPds(Condition cond, int32_t opcode, DRegister dd, SRegister sm) argument
3175 vmstat(Condition cond) argument
3241 SetItCondition(ItState s, Condition cond, uint8_t index) argument
3318 blx(Register rm, Condition cond) argument
3326 bx(Register rm, Condition cond) argument
3334 Push(Register rd, Condition cond) argument
3339 Pop(Register rd, Condition cond) argument
3344 PushList(RegList regs, Condition cond) argument
3349 PopList(RegList regs, Condition cond) argument
3378 Mov(Register rd, Register rm, Condition cond) argument
3414 Lsl(Register rd, Register rm, uint32_t shift_imm, Condition cond, SetCc set_cc) argument
3422 Lsr(Register rd, Register rm, uint32_t shift_imm, Condition cond, SetCc set_cc) argument
3431 Asr(Register rd, Register rm, uint32_t shift_imm, Condition cond, SetCc set_cc) argument
3440 Ror(Register rd, Register rm, uint32_t shift_imm, Condition cond, SetCc set_cc) argument
3448 Rrx(Register rd, Register rm, Condition cond, SetCc set_cc) argument
3454 Lsl(Register rd, Register rm, Register rn, Condition cond, SetCc set_cc) argument
3461 Lsr(Register rd, Register rm, Register rn, Condition cond, SetCc set_cc) argument
3468 Asr(Register rd, Register rm, Register rn, Condition cond, SetCc set_cc) argument
3475 Ror(Register rd, Register rm, Register rn, Condition cond, SetCc set_cc) argument
3629 AddConstant(Register rd, Register rn, int32_t value, Condition cond, SetCc set_cc) argument
3669 CmpConstant(Register rn, int32_t value, Condition cond) argument
3699 LoadImmediate(Register rd, int32_t value, Condition cond) argument
3714 LoadDImmediate(DRegister dd, double value, Condition cond) argument
3783 AdjustLoadStoreOffset(int32_t allowed_offset_bits, Register temp, Register base, int32_t offset, Condition cond) argument
3802 LoadFromOffset(LoadOperandType type, Register reg, Register base, int32_t offset, Condition cond) argument
3856 LoadSFromOffset(SRegister reg, Register base, int32_t offset, Condition cond) argument
3872 LoadDFromOffset(DRegister reg, Register base, int32_t offset, Condition cond) argument
3888 StoreToOffset(StoreOperandType type, Register reg, Register base, int32_t offset, Condition cond) argument
3944 StoreSToOffset(SRegister reg, Register base, int32_t offset, Condition cond) argument
3960 StoreDToOffset(DRegister reg, Register base, int32_t offset, Condition cond) argument
[all...]
H A Dassembler_arm_test.h91 std::vector<Cond>& cond = GetConditions(); local
93 WarnOnCombinations(cond.size() * immediates1.size() * immediates2.size() *
98 for (Cond& c : cond) {
182 std::vector<Cond>& cond = GetConditions(); local
184 WarnOnCombinations(cond.size() * immediates.size() * reg1_registers.size() *
189 for (Cond& c : cond) {
267 const std::vector<Cond>& cond,
271 WarnOnCombinations(cond.size() * reg1_registers.size() * reg2_registers.size());
275 for (const Cond& c : cond) {
331 const std::vector<Cond>& cond,
264 RepeatTemplatedRRC(void (Ass::*f)(Reg1, Reg2, Cond), const std::vector<Reg1*>& reg1_registers, const std::vector<Reg2*>& reg2_registers, const std::vector<Cond>& cond, std::string (AssemblerArmTest::*GetName1)(const Reg1&), std::string (AssemblerArmTest::*GetName2)(const Reg2&), std::string fmt) argument
327 RepeatTemplatedRRRC(void (Ass::*f)(Reg1, Reg2, Reg3, Cond), const std::vector<Reg1*>& reg1_registers, const std::vector<Reg2*>& reg2_registers, const std::vector<Reg3*>& reg3_registers, const std::vector<Cond>& cond, std::string (AssemblerArmTest::*GetName1)(const Reg1&), std::string (AssemblerArmTest::*GetName2)(const Reg2&), std::string (AssemblerArmTest::*GetName3)(const Reg3&), std::string fmt) argument
395 RepeatTemplatedRSC(void (Ass::*f)(RegT, SOp, Cond), const std::vector<RegT*>& registers, const std::vector<SOp>& shifts, const std::vector<Cond>& cond, std::string (AssemblerArmTest::*GetName)(const RegT&), std::string fmt) argument
449 RepeatTemplatedRRSC(void (Ass::*f)(Reg1, Reg2, const SOp&, Cond), const std::vector<Reg1*>& reg1_registers, const std::vector<Reg2*>& reg2_registers, const std::vector<SOp>& shifts, const std::vector<Cond>& cond, std::string (AssemblerArmTest::*GetName1)(const Reg1&), std::string (AssemblerArmTest::*GetName2)(const Reg2&), std::string fmt) argument
[all...]
H A Dassembler_arm_vixl.cc427 vixl32::Condition cond) {
430 ___ mov(cond, rd, rn);
432 ___ add(cond, rd, rn, value);
476 void ArmVIXLMacroAssembler::B(vixl32::Condition cond, vixl32::Label* label, bool is_far_target) { argument
483 b(cond, Narrow, label);
490 MacroAssembler::B(cond, label);
424 AddConstantInIt(vixl32::Register rd, vixl32::Register rn, int32_t value, vixl32::Condition cond) argument
H A Dassembler_arm_vixl.h135 // jumping within 2KB range. For B(cond, label), because the supported branch range is 256
137 void B(vixl32::Condition cond, vixl32::Label* label, bool is_far_target = true);
226 vixl32::Condition cond = vixl32::al);
/art/test/112-double-math/src/
H A DMain.java18 public static double cond_neg_double(double value, boolean cond) { argument
19 return cond ? -value : value;
/art/test/476-checker-ctor-memory-barrier/src/
H A DMain.java30 public ClassWithFinals(boolean cond) { argument
75 public InheritFromClassWithFinals(boolean cond) { argument
76 super(cond);
115 public HaveFinalsAndInheritFromClassWithFinals(boolean cond) { argument
116 super(cond);
/art/test/570-checker-select/src/
H A DMain.java39 public static int BoolCond_IntVarVar(boolean cond, int x, int y) { argument
44 return cond ? x : y;
65 public static int BoolCond_IntVarCst(boolean cond, int x) { argument
70 return cond ? x : 1;
91 public static int BoolCond_IntCstVar(boolean cond, int y) { argument
96 return cond ? 1 : y;
118 public static long BoolCond_LongVarVar(boolean cond, long x, long y) { argument
123 return cond ? x : y;
145 public static long BoolCond_LongVarCst(boolean cond, long x) { argument
150 return cond
172 BoolCond_LongCstVar(boolean cond, long y) argument
188 BoolCond_FloatVarVar(boolean cond, float x, float y) argument
204 BoolCond_FloatVarCst(boolean cond, float x) argument
220 BoolCond_FloatCstVar(boolean cond, float y) argument
583 BoolCond_0_m1(boolean cond) argument
611 BoolCond_m1_0(boolean cond) argument
[all...]
/art/test/450-checker-types/src/
H A DMain.java34 public int $inline$h(boolean cond) { argument
35 Super obj = (cond ? this : null);
549 private void updateNodesInTheSameBlockAsPhi(boolean cond) { argument
551 if (cond) {
595 private SuperInterface getWiderType(boolean cond, Interface a, OtherInterface b) { argument
596 return cond ? a : b;
608 private void testInlinerWidensReturnType(boolean cond, Interface a, OtherInterface b) { argument
609 getWiderType(cond, a, b).superInterfaceMethod();
639 public void testThisArgumentMoreSpecific(boolean cond) { argument
643 ((Super) obj).$inline$h(cond);
680 testPhiHasOnlyNullInputs(boolean cond) argument
692 testLoopPhiWithNullFirstInput(boolean cond) argument
[all...]
/art/runtime/interpreter/mterp/arm64/
H A Dfcmp.S1 %default {"wide":"", "r1":"s1", "r2":"s2", "cond":"lt"}
15 cneg w0, w0, $cond
/art/compiler/optimizing/
H A Dpc_relative_fixups_x86.cc108 void VisitEqual(HEqual* cond) OVERRIDE {
109 BinaryFP(cond); variable
112 void VisitNotEqual(HNotEqual* cond) OVERRIDE {
113 BinaryFP(cond); variable
116 void VisitLessThan(HLessThan* cond) OVERRIDE {
117 BinaryFP(cond); variable
120 void VisitLessThanOrEqual(HLessThanOrEqual* cond) OVERRIDE {
121 BinaryFP(cond); variable
124 void VisitGreaterThan(HGreaterThan* cond) OVERRIDE {
125 BinaryFP(cond); variable
129 BinaryFP(cond); variable
[all...]
H A Dbounds_check_elimination.cc629 IfCondition cond,
649 if (cond == kCondLT) {
653 } else if (cond == kCondLE) {
655 } else if (cond == kCondGT) {
657 } else if (cond == kCondGE) {
692 void HandleIf(HIf* instruction, HInstruction* left, HInstruction* right, IfCondition cond) { argument
730 HandleIfBetweenTwoMonotonicValueRanges(instruction, left, right, cond,
745 if (cond == kCondLT || cond == kCondLE) {
747 int32_t compensation = (cond
626 HandleIfBetweenTwoMonotonicValueRanges(HIf* instruction, HInstruction* left, HInstruction* right, IfCondition cond, MonotonicValueRange* left_range, MonotonicValueRange* right_range) argument
976 HCondition* cond = instruction->InputAt(0)->AsCondition(); variable
1551 HInstruction* cond = local
[all...]
H A Dcode_generator_mips.h287 void GenerateIntCompare(IfCondition cond, LocationSummary* locations);
291 bool MaterializeIntCompare(IfCondition cond,
294 void GenerateIntCompareAndBranch(IfCondition cond,
297 void GenerateLongCompareAndBranch(IfCondition cond,
300 void GenerateFpCompare(IfCondition cond,
307 bool MaterializeFpCompareR2(IfCondition cond,
315 bool MaterializeFpCompareR6(IfCondition cond,
320 void GenerateFpCompareAndBranch(IfCondition cond,
H A Dbounds_check_elimination_test.cc362 IfCondition cond = kCondGE) {
395 if (cond == kCondGE) {
398 DCHECK(cond == kCondGT);
477 IfCondition cond = kCondLE) {
513 if (cond == kCondLE) {
516 DCHECK(cond == kCondLT);
587 IfCondition cond) {
621 if (cond == kCondGE) {
624 DCHECK(cond == kCondGT);
688 IfCondition cond
583 BuildSSAGraph3(HGraph* graph, ArenaAllocator* allocator, int initial, int increment, IfCondition cond) argument
[all...]
H A Dcode_generator_arm_vixl.cc1374 inline vixl32::Condition ARMCondition(IfCondition cond) { argument
1375 switch (cond) {
1392 inline vixl32::Condition ARMUnsignedCondition(IfCondition cond) { argument
1393 switch (cond) {
1411 inline vixl32::Condition ARMFPCondition(IfCondition cond, bool gt_bias) { argument
1416 switch (cond) {
1703 IfCondition cond = condition->GetCondition(); local
1707 std::swap(cond, opposite);
1720 switch (cond) {
1736 ret = std::make_pair(ARMUnsignedCondition(cond), ARMUnsignedConditio
1785 IfCondition cond = condition->GetCondition(); local
1853 IfCondition cond = condition->GetCondition(); local
2471 GenerateLongComparesAndJumps(HCondition* cond, vixl32::Label* true_label, vixl32::Label* false_label) argument
2576 const auto cond = GenerateTest(condition, invert, codegen_); local
2611 HInstruction* cond = instruction->InputAt(condition_input_index); local
2906 HandleCondition(HCondition* cond) argument
2937 HandleCondition(HCondition* cond) argument
5677 LoadFromShiftedRegOffset(Primitive::Type type, Location out_loc, vixl32::Register base, vixl32::Register reg_index, vixl32::Condition cond) argument
5712 StoreToShiftedRegOffset(Primitive::Type type, Location loc, vixl32::Register base, vixl32::Register reg_index, vixl32::Condition cond) argument
[all...]
H A Dcodegen_test.cc696 for (int cond = kCondFirst; cond <= kCondLast; cond++) {
697 TestComparison(static_cast<IfCondition>(cond), i, j, Primitive::kPrimInt, target_config);
708 for (int cond = kCondFirst; cond <= kCondLast; cond++) {
709 TestComparison(static_cast<IfCondition>(cond), i, j, Primitive::kPrimLong, target_config);
H A Dcode_generator_arm.cc1330 inline Condition ARMCondition(IfCondition cond) { argument
1331 switch (cond) {
1348 inline Condition ARMUnsignedCondition(IfCondition cond) { argument
1349 switch (cond) {
1367 inline Condition ARMFPCondition(IfCondition cond, bool gt_bias) { argument
1372 switch (cond) {
1616 IfCondition cond = condition->GetCondition(); local
1620 std::swap(cond, opposite);
1633 switch (cond) {
1643 ret = std::make_pair(ARMUnsignedCondition(cond), ARMUnsignedConditio
1687 IfCondition cond = condition->GetCondition(); local
1752 IfCondition cond = condition->GetCondition(); local
2436 GenerateLongComparesAndJumps(HCondition* cond, Label* true_label, Label* false_label) argument
2541 const auto cond = GenerateTest(condition, invert, codegen_); local
2575 HInstruction* cond = instruction->InputAt(condition_input_index); local
2790 std::pair<Condition, Condition> cond; local
2875 HandleCondition(HCondition* cond) argument
2906 HandleCondition(HCondition* cond) argument
5667 LoadFromShiftedRegOffset(Primitive::Type type, Location out_loc, Register base, Register reg_offset, Condition cond) argument
5702 StoreToShiftedRegOffset(Primitive::Type type, Location loc, Register base, Register reg_offset, Condition cond) argument
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/art/test/611-checker-simplify-if/src/
H A DMain.java230 boolean cond = false;
234 cond = true;
238 cond = true;
241 cond = false;
244 if (cond) {
/art/test/441-checker-inliner/src/
H A DMain.java142 public static int InlineWithControlFlow(boolean cond) { argument
147 if (cond) {
/art/compiler/utils/arm64/
H A Djni_macro_assembler_arm64.h176 void Jump(JNIMacroLabel* label, JNIMacroUnaryCondition cond, ManagedRegister test) OVERRIDE;
213 vixl::aarch64::Condition cond = vixl::aarch64::al);
224 vixl::aarch64::Condition cond = vixl::aarch64::al);
228 vixl::aarch64::Condition cond = vixl::aarch64::al);
H A Djni_macro_assembler_arm64.cc73 void Arm64JNIMacroAssembler::AddConstant(XRegister rd, int32_t value, Condition cond) { argument
74 AddConstant(rd, rd, value, cond);
80 Condition cond) {
81 if ((cond == al) || (cond == nv)) {
86 // rd = cond ? temp : rn
91 ___ Csel(reg_x(rd), temp, reg_x(rd), cond); local
196 void Arm64JNIMacroAssembler::LoadImmediate(XRegister dest, int32_t value, Condition cond) { argument
197 if ((cond == al) || (cond
77 AddConstant(XRegister rd, XRegister rn, int32_t value, Condition cond) argument
207 ___ Csel(reg_x(dest), temp, reg_x(dest), cond); local
209 ___ Csel(reg_x(dest), reg_x(XZR), reg_x(dest), cond); local
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