Searched refs:reg_d (Results 1 - 3 of 3) sorted by relevance

/art/compiler/utils/arm64/
H A Dmanaged_register_arm64_test.cc671 EXPECT_TRUE(vixl::aarch64::d0.Is(Arm64Assembler::reg_d(D0)));
672 EXPECT_TRUE(vixl::aarch64::d1.Is(Arm64Assembler::reg_d(D1)));
673 EXPECT_TRUE(vixl::aarch64::d2.Is(Arm64Assembler::reg_d(D2)));
674 EXPECT_TRUE(vixl::aarch64::d3.Is(Arm64Assembler::reg_d(D3)));
675 EXPECT_TRUE(vixl::aarch64::d4.Is(Arm64Assembler::reg_d(D4)));
676 EXPECT_TRUE(vixl::aarch64::d5.Is(Arm64Assembler::reg_d(D5)));
677 EXPECT_TRUE(vixl::aarch64::d6.Is(Arm64Assembler::reg_d(D6)));
678 EXPECT_TRUE(vixl::aarch64::d7.Is(Arm64Assembler::reg_d(D7)));
679 EXPECT_TRUE(vixl::aarch64::d8.Is(Arm64Assembler::reg_d(D8)));
680 EXPECT_TRUE(vixl::aarch64::d9.Is(Arm64Assembler::reg_d(D
[all...]
H A Dassembler_arm64.h128 static vixl::aarch64::FPRegister reg_d(int code) {
H A Djni_macro_assembler_arm64.cc38 #define reg_d(D) Arm64Assembler::reg_d(D) macro
124 ___ Str(reg_d(source), MEM_OP(reg_x(base), offset));
251 ___ Ldr(reg_d(dest), MEM_OP(reg_x(base), offset));
278 ___ Ldr(reg_d(dest.AsDRegister()), MEM_OP(reg_x(base), offset));
356 ___ Fmov(reg_d(dst.AsDRegister()), reg_d(src.AsDRegister()));
700 fp_reg_list.Combine(reg_d(reg.AsDRegister()).GetCode());
756 fp_reg_list.Combine(reg_d(reg.AsDRegister()).GetCode());

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