Searched refs:FPU_MVFR0_Divide_Pos (Results 1 - 2 of 2) sorted by relevance

/device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
H A Dcore_cm4.h1258 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ macro
1259 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
H A Dcore_cm7.h1443 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ macro
1444 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */

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