Searched refs:MPU_RNR_REGION_Pos (Results 1 - 6 of 6) sorted by relevance

/device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
H A Dcore_cm0plus.h540 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ macro
541 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
H A Dcore_sc000.h559 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ macro
560 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
H A Dcore_cm3.h1096 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ macro
1097 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
H A Dcore_cm4.h1136 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ macro
1137 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
H A Dcore_sc300.h1076 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ macro
1077 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
H A Dcore_cm7.h1320 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ macro
1321 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */

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