/device/linaro/bootloader/edk2/AppPkg/Applications/Python/Python-2.7.2/Lib/test/ |
H A D | test_tempfile.py | 36 class TC(unittest.TestCase):
class in inherits:unittest.TestCase 65 class test_exports(TC):
94 class test__RandomNameSequence(TC):
132 class test__candidate_tempdir_list(TC):
177 class test__get_candidate_names(TC):
195 class test__mkstemp_inner(TC):
314 class test_gettempprefix(TC):
346 class test_gettempdir(TC):
381 class test_mkstemp(TC):
422 class test_mkdtemp(TC) [all...] |
/device/linaro/bootloader/edk2/Nt32Pkg/Sec/ |
H A D | SecMain.inf | 74 MSFT:*_*_IA32_PP_FLAGS == /nologo /E /TC /FIAutoGen.h
82 MSFT:*_*_X64_PP_FLAGS == /nologo /E /TC /FIAutoGen.h
88 INTEL:*_*_IA32_PP_FLAGS == /nologo /E /TC /FIAutoGen.h
|
/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/Include/Omap3530/ |
H A D | Omap3530MMCHS.h | 113 #define TC BIT1
macro
|
/device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/ |
H A D | Omap3530MMCHS.h | 113 #define TC BIT1
macro
|
/device/linaro/bootloader/edk2/SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/ |
H A D | DebugCommunicationLibUsb3Internal.h | 326 UINT32 TC:1;
member in struct:_LINK_TRB
|
H A D | DebugCommunicationLibUsb3Transfer.c | 51 ASSERT (((LINK_TRB*)TrsTrb)->TC != 0);
|
H A D | DebugCommunicationLibUsb3Common.c | 468 // Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.
470 EndTrb->TC = 1;
|
/device/linaro/bootloader/edk2/NetworkPkg/DnsDxe/ |
H A D | DnsImpl.h | 140 UINT16 TC:1;
member in struct:_DNS_FLAGS::__anon8390
|
/device/linaro/bootloader/OpenPlatformPkg/Chips/TexasInstruments/Omap35xx/MMCHSDxe/ |
H A D | MMCHS.c | 883 //Check if Transfer complete (TC) bit is set?
884 if (MmcStatus & TC) {
887 DEBUG ((EFI_D_ERROR, "MmcStatus for TC: %x\n", MmcStatus));
977 //Check if Transfer complete (TC) bit is set?
978 if (MmcStatus & TC) {
981 DEBUG ((EFI_D_ERROR, "MmcStatus for TC: %x\n", MmcStatus));
|
/device/linaro/bootloader/edk2/Omap35xxPkg/MMCHSDxe/ |
H A D | MMCHS.c | 883 //Check if Transfer complete (TC) bit is set?
884 if (MmcStatus & TC) {
887 DEBUG ((EFI_D_ERROR, "MmcStatus for TC: %x\n", MmcStatus));
977 //Check if Transfer complete (TC) bit is set?
978 if (MmcStatus & TC) {
981 DEBUG ((EFI_D_ERROR, "MmcStatus for TC: %x\n", MmcStatus));
|
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciPei/ |
H A D | XhciSched.h | 546 UINT32 TC:1;
member in struct:_LINK_TRB
|
H A D | XhciSched.c | 2677 ASSERT (((LINK_TRB *) TrsTrb)->TC != 0);
2749 // Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.
2751 EndTrb->TC = 1;
|
/device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/XhciDxe/ |
H A D | XhciSched.h | 550 UINT32 TC:1;
member in struct:_LINK_TRB
|
H A D | XhciSched.c | 889 // Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.
891 EndTrb->TC = 1;
1809 ASSERT (((LINK_TRB*)TrsTrb)->TC != 0);
|