Searched refs:AddrMode (Results 1 - 25 of 87) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Transforms/Utils/
H A DAddrModeMatcher.cpp65 /// Return true and update AddrMode if this addr mode is legal for the target,
80 if (AddrMode.Scale != 0 && AddrMode.ScaledReg != ScaleReg)
83 ExtAddrMode TestAddrMode = AddrMode;
95 AddrMode = TestAddrMode;
97 // Okay, we decided that we can add ScaleReg+Scale to AddrMode. Check now
110 AddrMode = TestAddrMode;
152 /// mode and return true, otherwise return false without modifying AddrMode.
181 ExtAddrMode BackupAddrMode = AddrMode;
188 AddrMode
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/external/swiftshader/third_party/LLVM/include/llvm/Transforms/Utils/
H A DAddrModeMatcher.h34 /// ExtAddrMode - This is an extended version of TargetLowering::AddrMode
36 struct ExtAddrMode : public TargetLowering::AddrMode {
64 /// AddrMode - This is the addressing mode that we're building up. This is
66 ExtAddrMode &AddrMode; member in class:llvm::AddressingModeMatcher
76 : AddrModeInsts(AMI), TLI(T), AccessTy(AT), MemoryInst(MI), AddrMode(AM) {
/external/llvm/lib/CodeGen/
H A DCodeGenPrepare.cpp2081 /// This is an extended version of TargetLowering::AddrMode
2083 struct ExtAddrMode : public TargetLowering::AddrMode {
2597 ExtAddrMode &AddrMode; member in class:__anon12533::AddressingModeMatcher
2620 MemoryInst(MI), AddrMode(AM), InsertedInsts(InsertedInsts),
2662 /// Return true and update AddrMode if this addr mode is legal for the target,
2677 if (AddrMode.Scale != 0 && AddrMode.ScaledReg != ScaleReg)
2680 ExtAddrMode TestAddrMode = AddrMode;
2692 AddrMode = TestAddrMode;
2694 // Okay, we decided that we can add ScaleReg+Scale to AddrMode
3724 ExtAddrMode AddrMode; local
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DThumb2InstrInfo.cpp390 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
395 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
465 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
471 if (AddrMode == ARMII::AddrModeT2_so) {
481 AddrMode = ARMII::AddrModeT2_i12;
486 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
500 } else if (AddrMode == ARMII::AddrMode5) {
531 if (AddrMode
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H A DARMBaseRegisterInfo.cpp894 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); local
898 switch (AddrMode) {
1085 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); local
1094 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
1100 switch (AddrMode) {
H A DARMISelLowering.h274 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
275 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
/external/swiftshader/third_party/LLVM/lib/Transforms/Scalar/
H A DCodeGenPrepare.cpp732 ExtAddrMode AddrMode; local
762 AddrMode = NewAddrMode;
765 } else if (NewAddrMode == AddrMode) {
805 DEBUG(dbgs() << "CGP: Found local addrmode: " << AddrMode << "\n");
820 DEBUG(dbgs() << "CGP: Reusing nonlocal addrmode: " << AddrMode << " for "
825 DEBUG(dbgs() << "CGP: SINKING nonlocal addrmode: " << AddrMode << " for "
837 if (AddrMode.BaseReg) {
838 Value *V = AddrMode.BaseReg;
847 if (AddrMode.Scale) {
848 Value *V = AddrMode
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/external/vixl/src/aarch32/
H A Doperands-aarch32.h651 explicit MemOperand(Register rn, AddrMode addrmode = Offset)
668 MemOperand(Register rn, int32_t offset, AddrMode addrmode = Offset)
678 MemOperand(Register rn, Sign sign, int32_t offset, AddrMode addrmode = Offset)
695 MemOperand(Register rn, Sign sign, Register rm, AddrMode addrmode = Offset)
709 MemOperand(Register rn, Register rm, AddrMode addrmode = Offset)
729 AddrMode addrmode = Offset)
745 MemOperand(Register rn, Register rm, Shift shift, AddrMode addrmode = Offset)
768 AddrMode addrmode = Offset)
789 AddrMode addrmode = Offset)
813 AddrMode GetAddrMod
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/external/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.h69 bool isLegalFlatAddressingMode(const AddrMode &AM) const;
70 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
86 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
/external/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp458 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
463 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
533 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
539 if (AddrMode == ARMII::AddrModeT2_so) {
549 AddrMode = ARMII::AddrModeT2_i12;
554 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
568 } else if (AddrMode == ARMII::AddrMode5) {
582 } else if (AddrMode
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H A DARMBaseRegisterInfo.cpp452 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); local
456 switch (AddrMode) {
641 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); local
650 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
656 switch (AddrMode) {
/external/spirv-llvm/lib/SPIRV/libSPIRV/
H A DSPIRVValue.h308 :SPIRVValue(M, WC, OC, TheType, TheId), AddrMode(TheAddrMode),
313 SPIRVConstantSampler():SPIRVValue(OC), AddrMode(SPIRVSAM_Invalid),
317 return AddrMode;
331 SPIRVWord AddrMode; member in class:SPIRV::SPIRVConstantSampler
340 _SPIRV_DEF_ENCDEC5(Type, Id, AddrMode, Normalized, FilterMode)
/external/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.h57 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
/external/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMBaseInfo.h235 enum AddrMode { enum in namespace:llvm::ARMII
255 inline static const char *AddrModeToString(AddrMode addrmode) {
327 AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/
H A DARMBaseInfo.h218 enum AddrMode { enum in namespace:llvm::ARMII
238 inline static const char *AddrModeToString(AddrMode addrmode) {
310 AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
/external/llvm/lib/Target/AVR/
H A DAVRISelLowering.h82 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonBaseInfo.h83 enum AddrMode { enum in namespace:llvm::HexagonII
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
H A DSPUISelLowering.h181 virtual bool isLegalAddressingMode(const AddrMode &AM,
/external/vixl/src/aarch64/
H A Doperands-aarch64.h821 AddrMode addrmode = Offset);
830 MemOperand(Register base, const Operand& offset, AddrMode addrmode = Offset);
845 AddrMode GetAddrMode() const { return addrmode_; }
846 VIXL_DEPRECATED("GetAddrMode", AddrMode addrmode() const) {
887 AddrMode addrmode_;
H A Doperands-aarch64.cc376 MemOperand::MemOperand(Register base, int64_t offset, AddrMode addrmode)
425 MemOperand::MemOperand(Register base, const Operand& offset, AddrMode addrmode)
/external/llvm/lib/Target/XCore/
H A DXCoreISelLowering.h125 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
/external/swiftshader/third_party/LLVM/lib/Target/XCore/
H A DXCoreISelLowering.h103 virtual bool isLegalAddressingMode(const AddrMode &AM,
/external/v8/src/arm64/
H A Dsimulator-arm64.h666 AddrMode addrmode);
667 void LoadStorePairHelper(Instruction* instr, AddrMode addrmode);
669 AddrMode addrmode);
672 AddrMode addrmode);
/external/v8/src/arm/
H A Dassembler-arm.h551 explicit MemOperand(Register rn, int32_t offset = 0, AddrMode am = Offset);
556 explicit MemOperand(Register rn, Register rm, AddrMode am = Offset);
562 ShiftOp shift_op, int shift_imm, AddrMode am = Offset);
565 AddrMode am = Offset)) {
582 AddrMode am() const { return am_; }
594 AddrMode am_; // bits P, U, and W
606 explicit NeonMemOperand(Register rn, AddrMode am = Offset, int align = 0);
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h320 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
328 int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,

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