Searched refs:CacheLineSize (Results 1 - 11 of 11) sorted by relevance

/external/llvm/lib/Target/AArch64/
H A DAArch64Subtarget.cpp57 CacheLineSize = 64;
72 CacheLineSize = 128;
H A DAArch64Subtarget.h88 uint16_t CacheLineSize = 0; member in class:llvm::AArch64Subtarget
197 unsigned getCacheLineSize() const { return CacheLineSize; }
/external/compiler-rt/lib/esan/
H A Dworking_set.cpp43 static const u32 CacheLineSize = 64; member in namespace:__esan
195 CHECK(getFlags()->cache_line_size == CacheLineSize);
222 static const u32 KilobyteCachelines = (0x1 << 10) / CacheLineSize;
233 return NumOfCachelines * CacheLineSize;
/external/stressapptest/src/
H A Dsat.h138 int CacheLineSize();
H A Dsat.cc1417 line_size = CacheLineSize();
1487 int Sat::CacheLineSize() { function in class:Sat
/external/syslinux/efi32/include/efi/
H A Dpci22.h44 UINT8 CacheLineSize; member in struct:__anon19628
/external/syslinux/efi64/include/efi/
H A Dpci22.h44 UINT8 CacheLineSize; member in struct:__anon19805
/external/syslinux/gnu-efi/gnu-efi-3.0/inc/
H A Dpci22.h44 UINT8 CacheLineSize; member in struct:__anon20025
/external/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp27 CacheLineSize("ppc-loop-prefetch-cache-line", cl::Hidden, cl::init(64),
243 return CacheLineSize;
/external/valgrind/VEX/switchback/
H A Dswitchback.c16 CacheLineSize to the right value. Values we currently know of:
55 # define CacheLineSize 0/*irrelevant*/ macro
63 # define CacheLineSize 0/*irrelevant*/ macro
580 //vex_archinfo.ppc_icache_line_szB = CacheLineSize;
/external/syslinux/gpxe/src/include/gpxe/efi/IndustryStandard/
H A DPci22.h37 UINT8 CacheLineSize; member in struct:__anon20512

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