Searched refs:Legal (Results 1 - 25 of 56) sorted by relevance

123

/external/skia/tools/
H A Drandom_parse_path.cpp11 const struct Legal { struct
71 const Legal& legal = gLegal[index];
/external/icu/icu4c/source/test/intltest/
H A Dtransrt.cpp113 // Legal
116 class Legal { class
118 Legal() {} function in class:Legal
119 virtual ~Legal() {}
123 class LegalJamo : public Legal {
168 class LegalGreek : public Legal {
203 // Legal greek has breathing marks IFF there is a vowel or RHO at the start
344 Legal* legalSource; // NOT owned
365 Legal* adoptedLegal,
468 Legal* adoptedLega
[all...]
/external/skia/fuzz/
H A DFuzzParsePath.cpp16 static const struct Legal { struct
79 const Legal& legal = gLegal[index];
/external/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp69 setOperationAction(ISD::ADD, VecTys[i], Legal);
70 setOperationAction(ISD::SUB, VecTys[i], Legal);
71 setOperationAction(ISD::LOAD, VecTys[i], Legal);
72 setOperationAction(ISD::STORE, VecTys[i], Legal);
73 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
84 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
120 setOperationAction(ISD::MUL, MVT::i64, Legal);
160 setOperationAction(ISD::MUL, MVT::i32, Legal);
161 setOperationAction(ISD::MULHS, MVT::i32, Legal);
162 setOperationAction(ISD::MULHU, MVT::i32, Legal);
[all...]
/external/icu/android_icu4j/src/main/tests/android/icu/dev/test/translit/
H A DRoundTripTest.java128 .test(KATAKANA, "[" + HIRAGANA + LENGTH + "]", "[" + HALFWIDTH_KATAKANA + LENGTH + "]", this, new Legal());
136 .test("[a-zA-Z]", HIRAGANA, HIRAGANA_ITERATION, this, new Legal());
144 .test("[a-zA-Z]", KATAKANA, "[" + KATAKANA_ITERATION + HALFWIDTH_KATAKANA + "]", this, new Legal());
175 t.test("[a-zA-Z]", "[\uAC00-\uD7A4]", "", this, new Legal());
391 .test("[a-zA-Z\u0110\u0111\u02BA\u02B9]", "[\u0400-\u045F]", null, this, new Legal());
401 .test("[a-zA-Z\u02BE\u02BF]", ARABIC, "[a-zA-Z\u02BE\u02BF\u207F]", null, this, new Legal()); //
443 public static class LegalIndic extends Legal{
917 public static class Legal { class in class:RoundTripTest
921 public static class LegalJamo extends Legal {
962 public static class LegalThai extends Legal {
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/external/icu/icu4j/main/tests/translit/src/com/ibm/icu/dev/test/translit/
H A DRoundTripTest.java127 .test(KATAKANA, "[" + HIRAGANA + LENGTH + "]", "[" + HALFWIDTH_KATAKANA + LENGTH + "]", this, new Legal());
135 .test("[a-zA-Z]", HIRAGANA, HIRAGANA_ITERATION, this, new Legal());
143 .test("[a-zA-Z]", KATAKANA, "[" + KATAKANA_ITERATION + HALFWIDTH_KATAKANA + "]", this, new Legal());
174 t.test("[a-zA-Z]", "[\uAC00-\uD7A4]", "", this, new Legal());
390 .test("[a-zA-Z\u0110\u0111\u02BA\u02B9]", "[\u0400-\u045F]", null, this, new Legal());
400 .test("[a-zA-Z\u02BE\u02BF]", ARABIC, "[a-zA-Z\u02BE\u02BF\u207F]", null, this, new Legal()); //
442 public static class LegalIndic extends Legal{
916 public static class Legal { class in class:RoundTripTest
920 public static class LegalJamo extends Legal {
961 public static class LegalThai extends Legal {
[all...]
/external/llvm/lib/Transforms/Vectorize/
H A DLoopVectorize.cpp298 VectorTripCount(nullptr), Legal(nullptr), AddedSafetyChecks(false) {}
311 Legal = L;
604 LoopVectorizationLegality *Legal; member in class:__anon13460::InnerLoopVectorizer
1603 LoopInfo *LI, LoopVectorizationLegality *Legal,
1608 : TheLoop(L), PSE(PSE), LI(LI), Legal(Legal), TTI(TTI), TLI(TLI), DB(DB),
1708 LoopVectorizationLegality *Legal; member in class:__anon13460::LoopVectorizationCostModel
1910 auto II = Legal->getInductionVars()->find(IV);
1911 assert(II != Legal->getInductionVars()->end() && "IV is not an induction");
2122 if (Legal
1602 LoopVectorizationCostModel(Loop *L, PredicatedScalarEvolution &PSE, LoopInfo *LI, LoopVectorizationLegality *Legal, const TargetTransformInfo &TTI, const TargetLibraryInfo *TLI, DemandedBits *DB, AssumptionCache *AC, const Function *F, const LoopVectorizeHints *Hints) argument
5733 isGatherOrScatterLegal(Instruction *I, Value *Ptr, LoopVectorizationLegality *Legal) argument
5749 isLikelyComplexAddressComputation(Value *Ptr, LoopVectorizationLegality *Legal, ScalarEvolution *SE, const Loop *TheLoop) argument
5793 isStrideMul(Instruction *I, LoopVectorizationLegality *Legal) argument
[all...]
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp97 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
98 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
99 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
100 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
101 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
102 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
103 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
104 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
105 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
106 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
H A DSPUISelLowering.cpp131 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
235 setOperationAction(ISD::ROTR, MVT::i32, Expand /*Legal*/);
236 setOperationAction(ISD::ROTR, MVT::i16, Expand /*Legal*/);
239 setOperationAction(ISD::ROTL, MVT::i32, Legal);
240 setOperationAction(ISD::ROTL, MVT::i16, Legal);
249 setOperationAction(ISD::SHL, MVT::i64, Legal);
250 setOperationAction(ISD::SRL, MVT::i64, Legal);
251 setOperationAction(ISD::SRA, MVT::i64, Legal);
255 setOperationAction(ISD::MUL, MVT::i32, Legal);
256 setOperationAction(ISD::MUL, MVT::i64, Legal);
[all...]
/external/llvm/include/llvm/Target/
H A DTargetLowering.h90 Legal, // The target natively supports this operation.
488 /// legal (return 'Legal') or we need to promote it to a larger type (return
611 (getOperationAction(Op, VT) == Legal ||
620 (getOperationAction(Op, VT) == Legal ||
629 (getOperationAction(Op, VT) == Legal ||
651 getOperationAction(Op, VT) == Legal;
670 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
676 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
695 return isTypeLegal(ValVT) && getTruncStoreAction(ValVT, MemVT) == Legal;
702 (getTruncStoreAction(ValVT, MemVT) == Legal ||
[all...]
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDGPUISelLowering.cpp35 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
36 setOperationAction(ISD::FEXP2, MVT::f32, Legal);
37 setOperationAction(ISD::FRINT, MVT::f32, Legal);
H A DAMDILISelLowering.cpp180 setOperationAction(ISD::Constant , MVT::i64 , Legal);
194 setOperationAction(ISD::ConstantFP , MVT::f64 , Legal);
223 setOperationAction(ISD::ConstantFP , MVT::f32 , Legal);
224 setOperationAction(ISD::Constant , MVT::i32 , Legal);
H A DSIISelLowering.cpp44 setOperationAction(ISD::ADD, MVT::i64, Legal);
45 setOperationAction(ISD::ADD, MVT::i32, Legal);
/external/swiftshader/third_party/LLVM/include/llvm/Target/
H A DTargetLowering.h91 Legal, // The target natively supports this operation. enumerator in enum:llvm::TargetLowering::LegalizeAction
261 /// it is already legal (return 'Legal') or we need to promote it to a larger
382 (getOperationAction(Op, VT) == Legal ||
390 getOperationAction(Op, VT) == Legal;
407 return VT.isSimple() && getLoadExtAction(ExtType, VT) == Legal;
426 getTruncStoreAction(ValVT, MemVT) == Legal;
446 (getIndexedLoadAction(IdxMode, VT) == Legal ||
467 (getIndexedStoreAction(IdxMode, VT) == Legal ||
488 return getCondCodeAction(CC, VT) == Legal ||
1782 /// Most operations are Legal (ak
[all...]
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp193 // f32 and f64 cases are Legal, f80 case is not
211 // are Legal, f80 is custom lowered.
217 // f32 and f64 cases are Legal, f80 case is not
279 // (low) operations are left as Legal, as there are single-result
305 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
306 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
307 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
323 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16 , Legal);
324 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32 , Legal);
327 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Legal);
[all...]
/external/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp75 setOperationAction(ISD::ConstantFP, T, Legal);
88 setOperationAction(Op, T, Legal);
90 setOperationAction(ISD::FMINNAN, T, Legal);
91 setOperationAction(ISD::FMAXNAN, T, Legal);
137 setOperationAction(ISD::TRAP, MVT::Other, Legal);
/external/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp111 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Legal);
112 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i16, Legal);
116 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal);
117 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal);
121 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i8, Legal);
122 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i16, Legal);
221 setOperationAction(ISD::Constant, MVT::i32, Legal);
222 setOperationAction(ISD::Constant, MVT::i64, Legal);
223 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
224 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/PTX/
H A DPTXISelLowering.cpp82 //////////// Legal /////////////////
85 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
86 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
/external/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp220 setOperationAction(ISD::TRAP, MVT::Other, Legal);
231 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
272 if (getOperationAction(Opcode, VT) == Legal)
288 setOperationAction(ISD::LOAD, VT, Legal);
289 setOperationAction(ISD::STORE, VT, Legal);
290 setOperationAction(ISD::VSELECT, VT, Legal);
291 setOperationAction(ISD::BITCAST, VT, Legal);
292 setOperationAction(ISD::UNDEF, VT, Legal);
305 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal);
306 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Legal);
[all...]
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1515 setOperationAction(ISD::LOAD, MVT::v2i32, Legal);
1516 setOperationAction(ISD::STORE, MVT::v2i32, Legal);
1517 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Legal);
1518 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Legal);
1625 Subtarget->usePopc() ? Legal : Expand);
1645 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Legal);
1647 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Legal);
1654 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal);
1655 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Legal);
1720 setOperationAction(ISD::TRAP , MVT::Other, Legal);
[all...]
/external/doclava/res/assets/templates-sdk/
H A Dfooter.cs42 <a href="/legal.html">Legal</a>
H A Dcustomizations.cs238 <a href="<?cs var:toroot ?>legal.html">Legal</a>
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp161 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal);
162 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
163 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
164 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
175 setOperationAction(ISD::ROTL, MVT::i64, Legal);
176 setOperationAction(ISD::ROTR, MVT::i64, Legal);
182 setOperationAction(ISD::ROTL, MVT::i32, Legal);
183 setOperationAction(ISD::ROTR, MVT::i32, Legal);
236 setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
237 setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
H A DX86ISelLowering.cpp278 // f32 and f64 cases are Legal, f80 case is not
290 // are Legal, f80 is custom lowered.
301 // f32 and f64 cases are Legal, f80 case is not
348 // (low) operations are left as Legal, as there are single-result
372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal);
374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
463 setOperationAction(ISD::PREFETCH , MVT::Other, Legal);
522 setOperationAction(ISD::TRAP, MVT::Other, Legal);
792 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
[all...]
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
H A DPPCISelLowering.cpp92 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
94 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
95 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
96 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
100 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
101 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
[all...]

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