/external/llvm/lib/Transforms/Scalar/ |
H A D | LoadCombine.cpp | 1 //===- LoadCombine.cpp - Combine Adjacent Loads ---------------------------===// 38 #define LDCOMBINE_NAME "Combine Adjacent Loads" 122 for (auto &Loads : LoadMap) { 123 if (Loads.second.size() < 2) 125 std::sort(Loads.second.begin(), Loads.second.end(), 129 if (aggregateLoads(Loads.second)) 139 bool LoadCombine::aggregateLoads(SmallVectorImpl<LoadPOPPair> &Loads) { argument 140 assert(Loads.size() >= 2 && "Insufficient loads!"); 147 for (auto &L : Loads) { 183 combineLoads(SmallVectorImpl<LoadPOPPair> &Loads) argument [all...] |
/external/antlr/antlr-3.4/runtime/Ruby/lib/antlr3/template/ |
H A D | group-file.rb | 7 purpose: Loads the ANTLR recognition code for ANTLR Template Group files
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/external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
H A D | PTXSelectionDAGInfo.cpp | 59 SDValue Loads[MAX_LOADS_IN_LDM]; local 69 Loads[i] = DAG.getLoad(VT, dl, Chain, 74 TFOps[i] = Loads[i].getValue(1); 81 TFOps[i] = DAG.getStore(Chain, dl, Loads[i], 108 Loads[i] = DAG.getLoad(VT, dl, Chain, 112 TFOps[i] = Loads[i].getValue(1); 130 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.cpp | 57 SDValue Loads[MAX_LOADS_IN_LDM]; local 66 Loads[i] = DAG.getLoad(VT, dl, Chain, 71 TFOps[i] = Loads[i].getValue(1); 78 TFOps[i] = DAG.getStore(Chain, dl, Loads[i], 105 Loads[i] = DAG.getLoad(VT, dl, Chain, 109 TFOps[i] = Loads[i].getValue(1); 127 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
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/external/swiftshader/third_party/LLVM/lib/Transforms/Utils/ |
H A D | DemoteRegToStack.cpp | 64 std::map<BasicBlock*, Value*> Loads; local 67 Value *&V = Loads[PN->getIncomingBlock(i)];
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/external/libhevc/common/arm/ |
H A D | ihevc_sao_edge_offset_class3_chroma.s | 90 LDR r7,[sp,#0x40] @Loads wd 91 LDR r8,[sp,#0x44] @Loads ht 94 LDR r4,[sp,#0x28] @Loads pu1_src_top_left 99 LDR r5,[sp,#0x34] @Loads pu1_avail 100 LDR r6,[sp,#0x38] @Loads pi1_sao_offset_u 175 LDR r11,[sp,#0x110] @Loads pi1_sao_offset_v 247 LDR r14,[sp,#0x110] @Loads pi1_sao_offset_v 279 LDR r6,[sp,#0x110] @Loads pi1_sao_offset_v 294 LDR r7,[sp,#0x114] @Loads wd 296 LDR r5,[sp,#0x108] @Loads pu1_avai [all...] |
H A D | ihevc_sao_edge_offset_class3.s | 81 LDR r7,[sp,#0x3C] @Loads wd 83 LDR r8,[sp,#0x40] @Loads ht 86 LDR r4,[sp,#0x28] @Loads pu1_src_top_left 91 LDR r5,[sp,#0x34] @Loads pu1_avail 92 LDR r6,[sp,#0x38] @Loads pi1_sao_offset 224 LDR r7,[sp,#0xD0] @Loads wd 226 LDR r5,[sp,#0xC8] @Loads pu1_avail 241 LDR r4,[sp,#0xD4] @Loads ht 247 LDR r7,[sp,#0xD0] @Loads wd 256 LDR r8,[sp,#0xC0] @Loads *pu1_sr [all...] |
H A D | ihevc_sao_edge_offset_class2_chroma.s | 90 LDR r7,[sp,#0x40] @Loads wd 91 LDR r8,[sp,#0x44] @Loads ht 94 LDR r4,[sp,#0x28] @Loads pu1_src_top_left 101 LDR r5,[sp,#0x34] @Loads pu1_avail 102 LDR r6,[sp,#0x38] @Loads pi1_sao_offset_u 181 LDR r11,[sp,#0x110] @Loads pi1_sao_offset_v 256 LDR r14,[sp,#0x110] @Loads pi1_sao_offset_v 283 LDR r6,[sp,#0x110] @Loads pi1_sao_offset_v 301 LDR r5,[sp,#0x108] @Loads pu1_avail 302 LDR r7,[sp,#0x114] @Loads w [all...] |
H A D | ihevc_sao_edge_offset_class2.s | 81 LDR r7,[sp,#0x3C] @Loads wd 83 LDR r8,[sp,#0x40] @Loads ht 86 LDR r4,[sp,#0x28] @Loads pu1_src_top_left 93 LDR r5,[sp,#0x34] @Loads pu1_avail 94 LDR r6,[sp,#0x38] @Loads pi1_sao_offset 214 LDR r7,[sp,#0xD0] @Loads wd 216 LDR r5,[sp,#0xC8] @Loads pu1_avail 235 LDR r7,[sp,#0xD0] @Loads wd 245 LDR r4,[sp,#0xD4] @Loads ht 249 LDR r8,[sp,#0xC0] @Loads *pu1_sr [all...] |
H A D | ihevc_sao_band_offset_luma.s | 73 LDR r8,[sp,#56] @Loads ht 74 LDR r7,[sp,#52] @Loads wd 77 LDR r5,[sp,#44] @Loads sao_band_pos 80 LDR r4,[sp,#40] @Loads pu1_src_top_left 94 LDR r6,[sp,#48] @Loads pi1_sao_offset
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H A D | ihevc_sao_band_offset_chroma.s | 79 LDR r4,[sp,#40] @Loads pu1_src_top_left 80 LDR r10,[sp,#64] @Loads ht 82 LDR r9,[sp,#60] @Loads wd 97 LDR r5,[sp,#44] @Loads sao_band_pos_u 107 LDR r7,[sp,#52] @Loads pi1_sao_offset_u 150 LDR r6,[sp,#48] @Loads sao_band_pos_v 201 LDR r8,[sp,#56] @Loads pi1_sao_offset_v
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H A D | ihevc_sao_edge_offset_class1_chroma.s | 76 LDR r7,[sp,#60] @Loads wd 77 LDR r4,[sp,#40] @Loads pu1_src_top_left 78 LDR r5,[sp,#52] @Loads pu1_avail 79 LDR r6,[sp,#56] @Loads pi1_sao_offset_u 80 LDR r7,[sp,#60] @Loads pi1_sao_offset_v 81 LDR r8,[sp,#64] @Loads wd 82 LDR r9,[sp,#68] @Loads ht
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H A D | ihevc_sao_edge_offset_class0_chroma.s | 76 LDR r9,[sp,#64] @Loads wd 78 LDR r4,[sp,#40] @Loads pu1_src_top_left 81 LDR r10,[sp,#68] @Loads ht 85 LDR r7,[sp,#52] @Loads pu1_avail 89 LDR r8,[sp,#56] @Loads pi1_sao_offset_u 99 LDR r5,[sp,#60] @Loads pi1_sao_offset_v
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H A D | ihevc_sao_edge_offset_class0.s | 75 LDR r9,[sp,#60] @Loads wd 77 LDR r4,[sp,#40] @Loads pu1_src_top_left 81 LDR r10,[sp,#64] @Loads ht 85 LDR r7,[sp,#52] @Loads pu1_avail 91 LDR r8,[sp,#56] @Loads pi1_sao_offset
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H A D | ihevc_sao_edge_offset_class1.s | 74 LDR r7,[sp,#60] @Loads wd 75 LDR r4,[sp,#40] @Loads pu1_src_top_left 76 LDR r5,[sp,#52] @Loads pu1_avail 77 LDR r6,[sp,#56] @Loads pi1_sao_offset 78 LDR r8,[sp,#64] @Loads ht
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/external/libavc/common/arm/ |
H A D | ih264_iquant_itrans_recon_dc_a9.s | 123 ldr r5, [sp, #36] @Loads *pu2_iscal_mat 124 ldr r6, [sp, #40] @Loads *pu2_weigh_mat 130 ldr r7, [sp, #44] @Loads u4_qp_div_6 132 ldr r4, [sp, #32] @Loads out_strd 133 ldr r9, [sp, #52] @Loads iq_start_idx 140 ldrsheq r10, [r0] @ Loads signed halfword pi2_src[0], if r9==1 242 ldr r5, [sp, #28] @Loads *pu2_iscal_mat 243 ldr r6, [sp, #32] @Loads *pu2_weigh_mat 249 ldr r7, [sp, #36] @Loads u4_qp_div_6 251 ldr r4, [sp, #24] @Loads out_str [all...] |
H A D | ih264_inter_pred_luma_horz_qpel_a9q.s | 113 ldr r5, [sp, #104] @Loads ht 114 ldr r6, [sp, #108] @Loads wd 115 ldr r7, [sp, #116] @Loads dydx
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H A D | ih264_iquant_itrans_recon_a9.s | 123 ldr r7, [sp, #52] @Loads u4_qp_div_6 124 ldr r4, [sp, #40] @Loads out_strd 126 ldr r5, [sp, #44] @Loads *pu2_iscal_mat 128 ldr r6, [sp, #48] @Loads *pu2_weigh_mat 130 ldr r8, [sp, #60] @Loads iq_start_idx 145 ldrsheq r9, [r10] @ Loads signed halfword pi2_dc_ld_addr[0], if r8==1 303 ldr r7, [sp, #52] @Loads u4_qp_div_6 304 ldr r4, [sp, #40] @Loads out_strd 306 ldr r5, [sp, #44] @Loads *pu2_iscal_mat 307 ldr r6, [sp, #48] @Loads *pu2_weigh_ma [all...] |
/external/llvm/lib/Transforms/Utils/ |
H A D | DemoteRegToStack.cpp | 68 DenseMap<BasicBlock*, Value*> Loads; local 71 Value *&V = Loads[PN->getIncomingBlock(i)];
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/external/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.cpp | 158 SDValue Loads[6]; local 212 Loads[i] = DAG.getLoad(VT, dl, Chain, 217 TFOps[i] = Loads[i].getValue(1); 236 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
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/external/llvm/lib/Analysis/ |
H A D | AliasAnalysisEvaluator.cpp | 103 SetVector<Value *> Loads; local 114 Loads.insert(&*I); 178 for (Value *Load : Loads) {
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGSDNodes.cpp | 249 SmallVector<SDNode*, 4> Loads; local 253 Loads.push_back(BaseLoad); 259 Loads.push_back(Load); 268 SDNode *Lead = Loads[0]; 272 for (unsigned I = 1, E = Loads.size(); I != E; ++I) { 274 SDNode *Load = Loads[I];
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGSDNodes.cpp | 213 SmallVector<SDNode*, 4> Loads; local 217 Loads.push_back(BaseLoad); 223 Loads.push_back(Load); 232 SDNode *Lead = Loads[0]; 236 for (unsigned I = 1, E = Loads.size(); I != E; ++I) { 238 SDNode *Load = Loads[I];
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/external/swiftshader/third_party/LLVM/lib/Transforms/IPO/ |
H A D | ArgumentPromotion.cpp | 378 SmallVector<LoadInst*, 16> Loads; local 387 Loads.push_back(LI); 416 Loads.push_back(LI); 446 if (Loads.empty()) return true; // No users, this is a dead argument. 459 for (unsigned i = 0, e = Loads.size(); i != e; ++i) { 462 LoadInst *Load = Loads[i];
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/external/llvm/lib/CodeGen/ |
H A D | ScheduleDAGInstrs.cpp | 57 // When Stores and Loads maps (or NonAliasStores and NonAliasLoads) 877 Value2SUsMap Stores, Loads(1 /*TrueMemOrderLatency*/); 880 // or Loads, and have therefore their own 'NonAlias' 1018 addBarrierChain(Loads); 1045 addChainDependencies(SU, Loads); 1059 addChainDependencies(SU, (ThisMayAlias ? Loads : NonAliasLoads), V); 1072 addChainDependencies(SU, Loads, UnknownValue); 1081 Loads.insert(SU, UnknownValue); 1092 (ThisMayAlias ? Loads : NonAliasLoads).insert(SU, V); 1100 if (Stores.size() + Loads [all...] |