/external/llvm/lib/Target/PowerPC/ |
H A D | PPCVSXCopy.cpp | 57 MachineRegisterInfo &MRI) { 59 return RC->hasSubClassEq(MRI.getRegClass(Reg)); 67 bool IsVSReg(unsigned Reg, MachineRegisterInfo &MRI) { argument 68 return IsRegInClass(Reg, &PPC::VSRCRegClass, MRI); 71 bool IsVRReg(unsigned Reg, MachineRegisterInfo &MRI) { argument 72 return IsRegInClass(Reg, &PPC::VRRCRegClass, MRI); 75 bool IsF8Reg(unsigned Reg, MachineRegisterInfo &MRI) { argument 76 return IsRegInClass(Reg, &PPC::F8RCRegClass, MRI); 79 bool IsVSFReg(unsigned Reg, MachineRegisterInfo &MRI) { argument 80 return IsRegInClass(Reg, &PPC::VSFRCRegClass, MRI); 56 IsRegInClass(unsigned Reg, const TargetRegisterClass *RC, MachineRegisterInfo &MRI) argument 83 IsVSSReg(unsigned Reg, MachineRegisterInfo &MRI) argument 91 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local [all...] |
/external/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMAsmBackendDarwin.h | 18 const MCRegisterInfo &MRI; member in class:llvm::ARMAsmBackendDarwin 22 const MCRegisterInfo &MRI, MachO::CPUSubTypeARM st) 23 : ARMAsmBackend(T, TT, /* IsLittleEndian */ true), MRI(MRI), Subtype(st) { 21 ARMAsmBackendDarwin(const Target &T, const Triple &TT, const MCRegisterInfo &MRI, MachO::CPUSubTypeARM st) argument
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H A D | ARMMCTargetDesc.h | 60 const MCRegisterInfo &MRI, 64 const MCRegisterInfo &MRI, 67 MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI, 71 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI, 74 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI, 78 const MCRegisterInfo &MRI, 82 const MCRegisterInfo &MRI,
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64AdvSIMDScalarPass.cpp | 72 MachineRegisterInfo *MRI; member in class:__anon12801::AArch64AdvSIMDScalar 113 const MachineRegisterInfo *MRI) { 117 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); 122 const MachineRegisterInfo *MRI) { 124 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && 126 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) && 136 const MachineRegisterInfo *MRI, 153 MRI) && 154 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI)) 157 MRI) 112 isGPR64(unsigned Reg, unsigned SubReg, const MachineRegisterInfo *MRI) argument 121 isFPR64(unsigned Reg, unsigned SubReg, const MachineRegisterInfo *MRI) argument 135 getSrcFromCopy(MachineInstr *MI, const MachineRegisterInfo *MRI, unsigned &SubReg) argument [all...] |
/external/llvm/lib/Target/BPF/MCTargetDesc/ |
H A D | BPFMCTargetDesc.h | 39 const MCRegisterInfo &MRI, 42 const MCRegisterInfo &MRI, 45 MCAsmBackend *createBPFAsmBackend(const Target &T, const MCRegisterInfo &MRI, 47 MCAsmBackend *createBPFbeAsmBackend(const Target &T, const MCRegisterInfo &MRI,
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | SIAssignInterpRegs.cpp | 38 void AddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI, 90 MachineRegisterInfo &MRI = MF.getRegInfo(); local 97 !MRI.use_empty(InterpUse[interp_idx].regs[reg_idx]); 113 unsigned virt_reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass); 114 MRI.replaceRegWith(InterpUse[interp_idx].regs[reg_idx], virt_reg); 115 AddLiveIn(&MF, MRI, new_reg, virt_reg); 123 MachineRegisterInfo & MRI, 127 if (!MRI.isLiveIn(physReg)) { 128 MRI.addLiveIn(physReg, virtReg); 134 MRI 122 AddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI, unsigned physReg, unsigned virtReg) argument [all...] |
H A D | SIISelLowering.h | 33 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const; 35 MachineBasicBlock::iterator I, MachineRegisterInfo &MRI) const; 37 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const; 39 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCTargetDesc.h | 39 const MCRegisterInfo &MRI, 42 const MCRegisterInfo &MRI, 46 const MCRegisterInfo &MRI, 49 const MCRegisterInfo &MRI, 52 const MCRegisterInfo &MRI, 55 const MCRegisterInfo &MRI,
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/external/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyReplacePhysRegs.cpp | 66 MachineRegisterInfo &MRI = MF.getRegInfo(); local 73 MRI.leaveSSA(); 74 MRI.invalidateLiveness(); 85 for (auto I = MRI.reg_begin(PReg), E = MRI.reg_end(); I != E; ) { 89 VReg = MRI.createVirtualRegister(RC);
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H A D | WebAssemblyRegColoring.cpp | 63 static float computeWeight(const MachineRegisterInfo *MRI, argument 67 for (MachineOperand &MO : MRI->reg_nodbg_operands(VReg)) 86 MachineRegisterInfo *MRI = &MF.getRegInfo(); 93 unsigned NumVRegs = MRI->getNumVirtRegs(); 103 if (MRI->use_empty(VReg)) 108 LI->weight = computeWeight(MRI, MBFI, VReg); 119 [MRI](LiveInterval *LHS, LiveInterval *RHS) { 120 if (MRI->isLiveIn(LHS->reg) != MRI->isLiveIn(RHS->reg)) 121 return MRI [all...] |
H A D | WebAssemblyPrepareForLiveIntervals.cpp | 75 static bool HasArgumentDef(unsigned Reg, const MachineRegisterInfo &MRI) { argument 76 for (auto &Def : MRI.def_instructions(Reg)) 89 MachineRegisterInfo &MRI = MF.getRegInfo(); local 97 MRI.leaveSSA(); 106 for (unsigned i = 0, e = MRI.getNumVirtRegs(); i < e; ++i) { 110 if (MRI.use_nodbg_empty(Reg)) 114 if (HasArgumentDef(Reg, MRI))
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H A D | WebAssemblyOptimizeLiveIntervals.cpp | 70 MachineRegisterInfo &MRI = MF.getRegInfo(); local 74 MRI.leaveSSA(); 76 assert(MRI.tracksLiveness() && 81 for (unsigned i = 0, e = MRI.getNumVirtRegs(); i < e; ++i) { 83 if (MRI.reg_nodbg_empty(Reg))
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H A D | WebAssemblyPeephole.cpp | 60 MachineRegisterInfo &MRI) { 64 unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); 75 MachineRegisterInfo &MRI, 91 unsigned NewReg = MRI.createVirtualRegister(MRI.getRegClass(Reg)); 109 MachineRegisterInfo &MRI = MF.getRegInfo(); local 138 Changed |= MaybeRewriteToDrop(OldReg, NewReg, MO, MFI, MRI); 159 if (MRI.getRegClass(NewReg) != MRI 58 MaybeRewriteToDrop(unsigned OldReg, unsigned NewReg, MachineOperand &MO, WebAssemblyFunctionInfo &MFI, MachineRegisterInfo &MRI) argument 72 MaybeRewriteToFallthrough(MachineInstr &MI, MachineBasicBlock &MBB, const MachineFunction &MF, WebAssemblyFunctionInfo &MFI, MachineRegisterInfo &MRI, const WebAssemblyInstrInfo &TII, unsigned FallthroughOpc, unsigned CopyLocalOpc) argument [all...] |
H A D | WebAssemblyStoreResults.cpp | 80 const MachineRegisterInfo &MRI, 93 for (auto I = MRI.use_begin(FromReg), E = MRI.use_end(); I != E;) { 143 const MachineRegisterInfo &MRI, 148 return ReplaceDominatedUses(MBB, MI, FromReg, ToReg, MRI, MDT, LIS); 152 const MachineRegisterInfo &MRI, 174 if (MRI.getRegClass(FromReg) != MRI.getRegClass(ToReg)) 177 return ReplaceDominatedUses(MBB, MI, FromReg, ToReg, MRI, MDT, LIS); 186 MachineRegisterInfo &MRI local 78 ReplaceDominatedUses(MachineBasicBlock &MBB, MachineInstr &MI, unsigned FromReg, unsigned ToReg, const MachineRegisterInfo &MRI, MachineDominatorTree &MDT, LiveIntervals &LIS) argument 142 optimizeStore(MachineBasicBlock &MBB, MachineInstr &MI, const MachineRegisterInfo &MRI, MachineDominatorTree &MDT, LiveIntervals &LIS) argument 151 optimizeCall(MachineBasicBlock &MBB, MachineInstr &MI, const MachineRegisterInfo &MRI, MachineDominatorTree &MDT, LiveIntervals &LIS, const WebAssemblyTargetLowering &TLI, const TargetLibraryInfo &LibInfo) argument [all...] |
H A D | WebAssemblyFrameLowering.cpp | 87 MachineRegisterInfo &MRI = MF.getRegInfo(); local 89 MRI.getTargetRegisterInfo()->getPointerRegClass(MF); 90 unsigned Zero = MRI.createVirtualRegister(PtrRC); 91 unsigned Drop = MRI.createVirtualRegister(PtrRC); 133 auto &MRI = MF.getRegInfo(); local 139 MRI.getTargetRegisterInfo()->getPointerRegClass(MF); 140 unsigned Zero = MRI.createVirtualRegister(PtrRC); 141 unsigned SPReg = MRI.createVirtualRegister(PtrRC); 159 unsigned OffsetReg = MRI.createVirtualRegister(PtrRC); 186 auto &MRI local [all...] |
/external/llvm/lib/CodeGen/ |
H A D | RegAllocBase.cpp | 58 MRI = &vrm.getRegInfo(); 62 MRI->freezeReservedRegs(vrm.getMachineFunction()); 71 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { 73 if (MRI->reg_nodbg_empty(Reg)) 89 if (MRI->reg_nodbg_empty(VirtReg->reg)) { 103 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg)) 114 I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end(); 128 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front()); 139 if (MRI [all...] |
H A D | OptimizePHIs.cpp | 33 MachineRegisterInfo *MRI; member in class:__anon12593::OptimizePHIs 69 MRI = &Fn.getRegInfo(); 107 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); 114 SrcMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg()); 147 for (MachineInstr &UseMI : MRI->use_instructions(DstReg)) { 171 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg))) 174 MRI->replaceRegWith(OldReg, SingleValReg);
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/external/llvm/lib/Target/AMDGPU/ |
H A D | SIFixSGPRCopies.cpp | 116 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); local 122 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) 131 const MachineRegisterInfo &MRI) { 137 MRI.getRegClass(SrcReg) : 145 MRI.getRegClass(DstReg) : 179 MachineRegisterInfo &MRI) { 183 if (!TRI->isSGPRClass(MRI.getRegClass(DstReg))) 186 if (!MRI.hasOneUse(DstReg)) 189 MachineInstr &CopyUse = *MRI.use_instr_begin(DstReg); 194 std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI); 129 getCopyRegClasses(const MachineInstr &Copy, const SIRegisterInfo &TRI, const MachineRegisterInfo &MRI) argument 176 foldVGPRCopyIntoRegSequence(MachineInstr &MI, const SIRegisterInfo *TRI, const SIInstrInfo *TII, MachineRegisterInfo &MRI) argument 241 MachineRegisterInfo &MRI = MF.getRegInfo(); local [all...] |
H A D | SIShrinkInstructions.cpp | 70 const MachineRegisterInfo &MRI) { 75 return TRI.hasVGPRs(MRI.getRegClass(MO->getReg())); 82 const MachineRegisterInfo &MRI) { 96 if (!isVGPR(Src2, TRI, MRI) || 110 if (Src1 && (!isVGPR(Src1, TRI, MRI) || (Src1Mod && Src1Mod->getImm() != 0))) 130 MachineRegisterInfo &MRI, bool TryToCommute = true) { 132 if (!MRI.isSSA()) 150 if (Src0.isReg() && !isVGPR(&Src0, TRI, MRI)) 154 if (Src0.isReg() && MRI.hasOneUse(Src0.getReg())) { 156 MachineInstr *Def = MRI 69 isVGPR(const MachineOperand *MO, const SIRegisterInfo &TRI, const MachineRegisterInfo &MRI) argument 80 canShrink(MachineInstr &MI, const SIInstrInfo *TII, const SIRegisterInfo &TRI, const MachineRegisterInfo &MRI) argument 129 foldImmediates(MachineInstr &MI, const SIInstrInfo *TII, MachineRegisterInfo &MRI, bool TryToCommute = true) argument [all...] |
/external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
H A D | AMDGPUMCTargetDesc.h | 39 const MCRegisterInfo &MRI, 43 const MCRegisterInfo &MRI, 46 MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI,
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | PHIEliminationUtils.cpp | 36 MachineRegisterInfo& MRI = MBB->getParent()->getRegInfo(); local 37 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(SrcReg), 38 RE = MRI.reg_end(); RI != RE; ++RI) {
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/external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
H A D | PTXMFInfoExtract.cpp | 53 MachineRegisterInfo &MRI = MF.getRegInfo(); local 56 for (unsigned i = 0; i < MRI.getNumVirtRegs(); ++i) { 58 const TargetRegisterClass *TRC = MRI.getRegClass(Reg);
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/external/llvm/lib/Target/AVR/MCTargetDesc/ |
H A D | AVRMCTargetDesc.h | 36 const MCRegisterInfo &MRI, 40 MCAsmBackend *createAVRAsmBackend(const Target &T, const MCRegisterInfo &MRI,
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXPeephole.cpp | 83 const auto &MRI = MF.getRegInfo(); local 86 GenericAddrDef = MRI.getUniqueVRegDef(Op.getReg()); 108 const auto &MRI = MF.getRegInfo(); local 110 auto &Prev = *MRI.getUniqueVRegDef(Root.getOperand(1).getReg()); 120 // Check if MRI has only one non dbg use, which is Root 121 if (MRI.hasOneNonDBGUse(Prev.getOperand(0).getReg())) { 147 const auto &MRI = MF.getRegInfo(); local 148 if (MRI.use_empty(NVPTX::VRFrame)) { 149 if (auto MI = MRI.getUniqueVRegDef(NVPTX::VRFrame)) {
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/external/mesa3d/src/gallium/drivers/radeon/InstPrinter/ |
H A D | AMDGPUInstPrinter.h | 14 const MCRegisterInfo &MRI) 15 : MCInstPrinter(MAI, MII, MRI) {} 13 AMDGPUInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
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