/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonCFGOptimizer.cpp | 75 int NewOpcode = 0; local 78 NewOpcode = Hexagon::J2_jumpf; 82 NewOpcode = Hexagon::J2_jumpt; 86 NewOpcode = Hexagon::J2_jumpfnewpt; 90 NewOpcode = Hexagon::J2_jumptnewpt; 97 MI.setDesc(TII->get(NewOpcode));
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H A D | HexagonVLIWPacketizer.cpp | 422 int NewOpcode; local 424 NewOpcode = HII->getDotNewPredOp(MI, MBPI); 426 NewOpcode = HII->getDotNewOp(MI); 427 MI->setDesc(HII->get(NewOpcode)); 432 int NewOpcode = HII->getDotOldOp(MI->getOpcode()); local 433 MI->setDesc(HII->get(NewOpcode)); 768 int NewOpcode = HII->getDotNewOp(MI); local 769 const MCInstrDesc &D = HII->get(NewOpcode);
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H A D | HexagonInstrInfo.cpp | 1333 unsigned NewOpcode = getInvertedPredicatedOpcode(opcode); local 1334 Cond[0].setImm(NewOpcode); 3601 int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode()); local 3602 if (NewOpcode >= 0) // Valid predicate new instruction 3603 return NewOpcode; 4231 unsigned NewOpcode = getInvertedPredicatedOpcode(MI->getOpcode()); local 4240 NewOpcode = reversePrediction(NewOpcode); 4242 MI->setDesc(get(NewOpcode));
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/external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
H A D | XCoreRegisterInfo.cpp | 286 int NewOpcode; local 288 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; 289 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) 293 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; 294 BuildMI(MBB, II, dl, TII.get(NewOpcode)) 299 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; 300 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreRegisterInfo.cpp | 138 int NewOpcode; local 140 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; 141 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) 146 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; 147 BuildMI(MBB, II, dl, TII.get(NewOpcode)) 153 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; 154 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
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/external/llvm/lib/Target/X86/ |
H A D | X86FixupLEAs.cpp | 273 int NewOpcode; local 277 NewOpcode = isINC ? X86::INC16r : X86::DEC16r; 281 NewOpcode = isINC ? X86::INC32r : X86::DEC32r; 284 NewOpcode = isINC ? X86::INC64r : X86::DEC64r; 289 BuildMI(*MFI, I, MI.getDebugLoc(), TII->get(NewOpcode))
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H A D | X86MCInstLower.cpp | 275 unsigned NewOpcode = 0; local 282 NewOpcode = X86::CBW; 286 NewOpcode = X86::CWDE; 290 NewOpcode = X86::CDQE; 294 if (NewOpcode != 0) { 296 Inst.setOpcode(NewOpcode);
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H A D | X86InstrInfo.cpp | 5049 unsigned NewOpcode = 0; local 5072 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break; 5073 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break; 5074 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break; 5075 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break; 5076 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break; 5077 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break; 5078 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break; 5079 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break; 5080 case X86::SUB64ri32: NewOpcode [all...] |
/external/llvm/lib/Target/AMDGPU/ |
H A D | AMDILCFGStructurizer.cpp | 228 void insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode, 230 MachineInstr *insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode, 232 MachineInstr *insertInstrBefore(MachineBasicBlock::iterator I, int NewOpcode); 233 void insertCondBranchBefore(MachineBasicBlock::iterator I, int NewOpcode, 236 MachineBasicBlock::iterator I, int NewOpcode, 454 int NewOpcode, const DebugLoc &DL) { 456 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); 463 int NewOpcode, 466 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); 476 MachineBasicBlock::iterator I, int NewOpcode) { 453 insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode, const DebugLoc &DL) argument 462 insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode, const DebugLoc &DL) argument 475 insertInstrBefore( MachineBasicBlock::iterator I, int NewOpcode) argument 487 insertCondBranchBefore( MachineBasicBlock::iterator I, int NewOpcode, const DebugLoc &DL) argument 500 insertCondBranchBefore( MachineBasicBlock *blk, MachineBasicBlock::iterator I, int NewOpcode, int RegNum, const DebugLoc &DL) argument [all...] |
H A D | SIInstrInfo.cpp | 2506 unsigned NewOpcode = getVALUOp(Inst); 2545 NewOpcode = AMDGPU::V_LSHLREV_B32_e64; 2551 NewOpcode = AMDGPU::V_ASHRREV_I32_e64; 2557 NewOpcode = AMDGPU::V_LSHRREV_B32_e64; 2563 NewOpcode = AMDGPU::V_LSHLREV_B64; 2569 NewOpcode = AMDGPU::V_ASHRREV_I64; 2575 NewOpcode = AMDGPU::V_LSHRREV_B64; 2599 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) { 2607 const MCInstrDesc &NewDesc = get(NewOpcode);
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H A D | SIISelLowering.cpp | 3262 unsigned NewOpcode = TII->getMaskedMIMGOp(MI.getOpcode(), BitsSet); local 3263 MI.setDesc(TII->get(NewOpcode));
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/external/llvm/lib/Target/Lanai/ |
H A D | LanaiRegisterInfo.cpp | 232 unsigned NewOpcode = getOppositeALULoOpcode(MI.getOpcode()); local 237 BuildMI(*MI.getParent(), II, DL, TII->get(NewOpcode),
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZFrameLowering.cpp | 458 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); local 462 if (!NewOpcode) { 467 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); 468 assert(NewOpcode && "No restore instruction available"); 471 MBBI->setDesc(ZII->get(NewOpcode));
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H A D | SystemZInstrInfo.cpp | 50 // each having the opcode given by NewOpcode. 52 unsigned NewOpcode) const { 79 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm()); 80 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm()); 97 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset); local 98 assert(NewOpcode && "No support for huge argument lists yet"); 99 MI->setDesc(get(NewOpcode)); 845 unsigned NewOpcode; local 847 NewOpcode = SystemZ::RISBG; 850 NewOpcode [all...] |
H A D | SystemZInstrInfo.h | 137 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCCodeEmitter.cpp | 231 int NewOpcode = -1; local 234 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6); 235 if (NewOpcode == -1) 236 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6); 239 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips); 242 if (NewOpcode == -1) 243 NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp); 245 if (NewOpcode != -1) { 249 Opcode = NewOpcode; 250 TmpInst.setOpcode (NewOpcode); [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 4175 unsigned NewOpcode; local 4179 case PPC::RLWINM: NewOpcode = PPC::RLWINM8; break; 4180 case PPC::RLWNM: NewOpcode = PPC::RLWNM8; break; 4181 case PPC::SLW: NewOpcode = PPC::SLW8; break; 4182 case PPC::SRW: NewOpcode = PPC::SRW8; break; 4183 case PPC::LI: NewOpcode = PPC::LI8; break; 4184 case PPC::LIS: NewOpcode = PPC::LIS8; break; 4185 case PPC::LHBRX: NewOpcode = PPC::LHBRX8; break; 4186 case PPC::LWBRX: NewOpcode = PPC::LWBRX8; break; 4187 case PPC::CNTLZW: NewOpcode [all...] |
H A D | PPCAsmPrinter.cpp | 967 unsigned NewOpcode = local 971 EmitToStreamer(*OutStreamer, MCInstBuilder(NewOpcode) 981 unsigned NewOpcode = local 987 EmitToStreamer(*OutStreamer, MCInstBuilder(NewOpcode)
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H A D | PPCRegisterInfo.cpp | 908 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; local 909 MI.setDesc(TII.get(NewOpcode));
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/external/llvm/lib/Target/PowerPC/AsmParser/ |
H A D | PPCAsmParser.cpp | 1670 std::string NewOpcode; local 1673 NewOpcode = Name; 1674 NewOpcode += '+'; 1675 Name = NewOpcode; 1679 NewOpcode = Name; 1680 NewOpcode += '-'; 1681 Name = NewOpcode; 1687 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. 1695 if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
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/external/llvm/lib/Target/Mips/ |
H A D | MipsDelaySlotFiller.cpp | 537 unsigned NewOpcode = TII->getEquivalentCompactForm(Branch); local 538 Branch = TII->genInstrWithNewOpc(NewOpcode, Branch);
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.cpp | 618 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; local 619 MI.setDesc(TII.get(NewOpcode));
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/external/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 2731 unsigned NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM32_MM : Mips::LWM32_MM; local 2745 NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MMR6 : Mips::LWM16_MMR6; 2747 NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MM : Mips::LWM16_MM; 2750 Inst.setOpcode(NewOpcode);
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 3119 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; local 3123 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3131 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; local 3135 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 4206 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; local 4210 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS); 4218 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; local 4222 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS);
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