| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| H A D | radeon_opcodes.c | 45 .NumSrcRegs = 1,
52 .NumSrcRegs = 2,
59 .NumSrcRegs = 1,
65 .NumSrcRegs = 1,
72 .NumSrcRegs = 3,
79 .NumSrcRegs = 3,
86 .NumSrcRegs = 3,
93 .NumSrcRegs = 1,
100 .NumSrcRegs = 2,
107 .NumSrcRegs
[all...] |
| H A D | radeon_opcodes.h | 252 unsigned int NumSrcRegs:2; member in struct:rc_opcode_info
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| H A D | radeon_pair_dead_sources.c | 25 for (i = 0; i < info->NumSrcRegs; i++) {
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| H A D | r3xx_vertprog.c | 529 for (unsigned i = 0; i < info->NumSrcRegs; i++)
570 for (i = 0; i < opcode->NumSrcRegs; ++i) {
617 for (i = 0; i < opcode->NumSrcRegs; ++i) {
628 for (i = 0; i < opcode->NumSrcRegs; ++i) {
671 for (i = 0; i < opcode->NumSrcRegs; i++) {
708 if (opcode->NumSrcRegs == 3) {
724 if (opcode->NumSrcRegs >= 2) {
814 for (unsigned i = 0; i < opcode->NumSrcRegs; i++)
838 for (unsigned i = 0; i < opcode->NumSrcRegs; i++) {
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| H A D | radeon_inline_literals.c | 81 for (src_idx = 0; src_idx < info->NumSrcRegs; src_idx++) {
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| H A D | radeon_program_pair.c | 177 for(i = 0; i < info->NumSrcRegs; i++) {
192 for(i = 0; i < info->NumSrcRegs; i++) {
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| H A D | r3xx_fragprog.c | 75 for (i = 0; i < info->NumSrcRegs; i++) {
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| H A D | radeon_compiler.c | 122 for (i = 0; i < opcode->NumSrcRegs; ++i) {
148 for(i = 0; i < opcode->NumSrcRegs; ++i) {
303 for(i = 0; i < opcode->NumSrcRegs; i++) {
347 for(i = 0; i < opcode->NumSrcRegs; i++) {
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| H A D | radeon_dataflow_swizzles.c | 98 for(src = 0; src < opcode->NumSrcRegs; ++src) {
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| H A D | radeon_program_print.c | 302 if (opcode->NumSrcRegs)
306 for(reg = 0; reg < opcode->NumSrcRegs; ++reg) {
404 for(unsigned int arg = 0; arg < opcode->NumSrcRegs; ++arg) {
439 for(unsigned int arg = 0; arg < opcode->NumSrcRegs; ++arg) {
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| H A D | radeon_pair_translate.c | 213 for(i = 0; i < opcode->NumSrcRegs; ++i) {
340 for (unsigned i = 0; i < opcode->NumSrcRegs; i++) {
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| H A D | radeon_dataflow_deadcode.c | 184 for(unsigned int src = 0; src < opcode->NumSrcRegs; ++src) {
258 for(src=0; src < opcode->NumSrcRegs; src++){
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| H A D | radeon_optimize.c | 315 for(unsigned int src = 0; src < opcode->NumSrcRegs; ++src) {
400 for(i = opcode->NumSrcRegs; i < 3; i++) {
474 for (src_index = 0; src_index < info->NumSrcRegs; src_index++) {
550 for(i = 0; i < info->NumSrcRegs; i++) {
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| H A D | radeon_compiler_util.c | 202 for (i = 0; i < info->NumSrcRegs; i++) {
562 for (i = 0; i < info->NumSrcRegs; i++) {
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| /external/mesa3d/src/gallium/auxiliary/draw/ |
| H A D | draw_pipe_aapoint.c | 246 newInst.Instruction.NumSrcRegs = 2;
260 newInst.Instruction.NumSrcRegs = 2;
277 newInst.Instruction.NumSrcRegs = 1;
289 newInst.Instruction.NumSrcRegs = 1;
302 newInst.Instruction.NumSrcRegs = 2;
315 newInst.Instruction.NumSrcRegs = 1;
335 newInst.Instruction.NumSrcRegs = 2;
351 newInst.Instruction.NumSrcRegs = 1;
364 newInst.Instruction.NumSrcRegs = 2;
380 newInst.Instruction.NumSrcRegs
[all...] |
| H A D | draw_pipe_pstipple.c | 296 newInst.Instruction.NumSrcRegs = 2;
309 newInst.Instruction.NumSrcRegs = 2;
322 newInst.Instruction.NumSrcRegs = 1;
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| H A D | draw_pipe_aaline.c | 282 newInst.Instruction.NumSrcRegs = 2;
299 newInst.Instruction.NumSrcRegs = 1;
311 newInst.Instruction.NumSrcRegs = 2;
322 newInst.Instruction.NumSrcRegs = 0;
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| /external/mesa3d/src/gallium/auxiliary/util/ |
| H A D | u_linkage.c | 96 for(i = 0; i < finst->Instruction.NumSrcRegs; ++i)
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| H A D | u_pstipple.c | 362 newInst.Instruction.NumSrcRegs = 2;
375 newInst.Instruction.NumSrcRegs = 2;
388 newInst.Instruction.NumSrcRegs = 1;
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| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| H A D | tgsi_parse.c | 239 assert( inst->Instruction.NumSrcRegs <= TGSI_FULL_MAX_SRC_REGISTERS );
241 for( i = 0; i < inst->Instruction.NumSrcRegs; i++ ) {
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| H A D | tgsi_sanity.c | 333 if (info->num_src != inst->Instruction.NumSrcRegs) {
351 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
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| H A D | tgsi_build.c | 592 instruction.NumSrcRegs = 1;
620 instruction.NumSrcRegs = num_src_regs;
983 full_inst->Instruction.NumSrcRegs,
1142 for( i = 0; i < full_inst->Instruction.NumSrcRegs; i++ ) {
|
| /external/mesa3d/src/mesa/program/ |
| H A D | prog_instruction.c | 146 GLuint NumSrcRegs; member in struct:instruction_info
262 return InstInfo[opcode].NumSrcRegs;
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| /external/mesa3d/src/gallium/drivers/r300/ |
| H A D | r300_vs_draw.c | 254 new_inst.Instruction.NumSrcRegs = 1;
266 new_inst.Instruction.NumSrcRegs = 1;
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| /external/mesa3d/src/gallium/include/pipe/ |
| H A D | p_shader_tokens.h | 445 * NumDstRegs and NumSrcRegs is the number of destination and source registers,
461 unsigned NumSrcRegs : 4; /* UINT */ member in struct:tgsi_instruction
477 * Then, tgsi_instruction::NumSrcRegs of tgsi_src_register follow.
|