/external/v8/tools/turbolizer/ |
H A D | lang-disassembly.js | 5 PR.registerLangHandler( 6 PR.createSimpleLexer( 8 [PR.PR_STRING, /^(?:\'(?:[^\\\'\r\n]|\\.)*(?:\'|$))/, null, '\''], 9 [PR.PR_PLAIN, /^\s+/, null, ' \r\n\t\xA0'] 12 [PR.PR_COMMENT, /;; debug: position \d+/, null],
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H A D | code-view.js | 8 constructor(divID, PR, sourceText, sourcePosition, broker) { 11 view.PR = PR; 134 view.PR.prettyPrint();
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/external/clang/test/SemaCXX/ |
H A D | access-control-check.cpp | 14 int PR() { return iP + PPR(); } // expected-error 2 {{private member of 'P'}} function in class:N
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/external/zlib/src/as400/ |
H A D | zlib.inc | 113 D compress PR 10I 0 extproc('compress') 119 D compress2 PR 10I 0 extproc('compress2') 126 D compressBound PR 10U 0 extproc('compressBound') 129 D uncompress PR 10I 0 extproc('uncompress') 136 D gzopen PR extproc('gzopen') 141 D gzopen PR extproc('gzopen64') 146 D gzopen64 PR extproc('gzopen64') 152 D gzdopen PR extproc('gzdopen') 157 D gzbuffer PR 10I 0 extproc('gzbuffer') 161 D gzsetparams PR 1 [all...] |
/external/clang/test/CodeGenCXX/ |
H A D | nested-base-member-access.cpp | 38 void PR() { function in struct:N 51 n1.PR();
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H A D | constructor-init.cpp | 36 void PR() { function in struct:N 61 n1.PR();
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXTargetMachine.cpp | 77 PassRegistry &PR = *PassRegistry::getPassRegistry(); local 78 initializeNVVMReflectPass(PR); 79 initializeNVVMIntrRangePass(PR); 80 initializeGenericToNVVMPass(PR); 81 initializeNVPTXAllocaHoistingPass(PR); 82 initializeNVPTXAssignValidGlobalNamesPass(PR); 83 initializeNVPTXFavorNonGenericAddrSpacesPass(PR); 84 initializeNVPTXInferAddressSpacesPass(PR); 85 initializeNVPTXLowerKernelArgsPass(PR); 86 initializeNVPTXLowerAllocaPass(PR); [all...] |
/external/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUTargetMachine.cpp | 75 PassRegistry *PR = PassRegistry::getPassRegistry(); local 76 initializeSILowerI1CopiesPass(*PR); 77 initializeSIFixSGPRCopiesPass(*PR); 78 initializeSIFoldOperandsPass(*PR); 79 initializeSIShrinkInstructionsPass(*PR); 80 initializeSIFixControlFlowLiveIntervalsPass(*PR); 81 initializeSILoadStoreOptimizerPass(*PR); 82 initializeAMDGPUAnnotateKernelFeaturesPass(*PR); 83 initializeAMDGPUAnnotateUniformValuesPass(*PR); 84 initializeAMDGPUPromoteAllocaPass(*PR); [all...] |
/external/clang/include/clang/Lex/ |
H A D | PreprocessingRecord.h | 35 void *operator new(size_t bytes, clang::PreprocessingRecord &PR, 39 void operator delete(void *ptr, clang::PreprocessingRecord &PR, 101 void *operator new(size_t bytes, PreprocessingRecord &PR, 103 return ::operator new(bytes, PR, alignment); 108 void operator delete(void *ptr, PreprocessingRecord &PR, 110 return ::operator delete(ptr, PR, alignment); 526 inline void *operator new(size_t bytes, clang::PreprocessingRecord &PR, 528 return PR.Allocate(bytes, alignment); 531 inline void operator delete(void *ptr, clang::PreprocessingRecord &PR, 533 PR [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 50 friend raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR); 55 raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR) 57 raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR) { argument 58 return OS << PrintReg(PR.Reg.R, &PR.TRI, PR.Reg.S); 239 Register PR = DefI->getOperand(1); local 240 G2P.insert(std::make_pair(Reg, PR)); 241 DEBUG(dbgs() << " -> " << PrintRegister(PR, *TRI) << '\n'); 242 return PR; 307 Register PR = WorkQ.front(); local 385 Register PR = getPredRegFor(MI->getOperand(1)); local [all...] |
H A D | HexagonGenMux.cpp | 76 MuxInfo(MachineBasicBlock::iterator It, unsigned DR, unsigned PR, argument 79 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1), 213 unsigned PR = MI->getOperand(1).getReg(); local 220 if (F != CM.end() && F->second.PredR != PR) { 227 F->second.PredR = PR; 248 if (!DU.Defs[PR]) 272 if (DU.Defs[PR] || DU.Defs[DR] || DU.Uses[DR]) { 289 ML.push_back(MuxInfo(At, DR, PR, SrcT, SrcF, Def1, Def2));
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H A D | HexagonPeephole.cpp | 265 unsigned PR = 1, S1 = 2, S2 = 3; // Operand indices. local 280 unsigned PSrc = MI.getOperand(PR).getReg(); 282 MI.getOperand(PR).setReg(POrig);
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCChecker.h | 106 static NewSense Use(unsigned PR, bool True) { argument 107 NewSense NS = { /*PredReg=*/ PR, /*IsFloat=*/ false, /*IsNVJ=*/ false, 111 static NewSense Def(unsigned PR, bool True, bool Float) { argument 112 NewSense NS = { /*PredReg=*/ PR, /*IsFloat=*/ Float, /*IsNVJ=*/ false,
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/external/icu/icu4c/source/test/testdata/break_rules/ |
H A D | line.txt | 50 PR = [:LineBreak = Prefix_Numeric:]; 162 LB23a.1: PR CM* (ID | EB | EM); 165 LB24.2: (PR | PO) CM* (AL | HL); 166 LB24.3: (AL | HL | CM) CM* (PR | PO); 169 LB25: ((PR | PO)CM*)? ((OP | HY)CM*)? NU (CM*(NU | SY | IS))* (CM*(CL | CP))? (CM*(PR | PO))?; 177 LB27.3: PR CM* (JL | JV | JT | H2 | H3);
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H A D | line_loose.txt | 58 PR = [:LineBreak = Prefix_Numeric:]; 170 LB23a.1: PR CM* (ID | EB | EM); 173 LB24.2: (PR | PO) CM* (AL | HL); 174 LB24.3: (AL | HL | CM) CM* (PR | PO); 177 LB25: ((PR | PO)CM*)? ((OP | HY)CM*)? NU (CM*(NU | SY | IS))* (CM*(CL | CP))? (CM*(PR | PO))?; 185 LB27.3: PR CM* (JL | JV | JT | H2 | H3);
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H A D | line_loose_cj.txt | 30 # * after prefix characters with LineBreak class PR and EastAsianWidth A,F,W; 75 PR = [[:LineBreak = Prefix_Numeric:] - PRX]; 190 LB23a.1: PR CM* (ID | EB | EM); 193 LB24.2: (PR | PO | POX) CM* (AL | HL); 194 LB24.3: (AL | HL | CM) CM* (PR | PO | POX); 198 LB25: ((PR | PO | POX)CM*)? ((OP | HY)CM*)? NU (CM*(NU | SY | IS))* (CM*(CL | CP))? (CM*(PR | PRX | PO))?; 206 LB27.3: PR CM* (JL | JV | JT | H2 | H3);
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H A D | line_normal.txt | 64 PR = [:LineBreak = Prefix_Numeric:]; 176 LB23a.1: PR CM* (ID | EB | EM); 179 LB24.2: (PR | PO) CM* (AL | HL); 180 LB24.3: (AL | HL | CM) CM* (PR | PO); 183 LB25: ((PR | PO)CM*)? ((OP | HY)CM*)? NU (CM*(NU | SY | IS))* (CM*(CL | CP))? (CM*(PR | PO))?; 191 LB27.3: PR CM* (JL | JV | JT | H2 | H3);
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H A D | line_normal_cj.txt | 66 PR = [:LineBreak = Prefix_Numeric:]; 185 LB23a.1: PR CM* (ID | EB | EM); 188 LB24.2: (PR | PO) CM* (AL | HL); 189 LB24.3: (AL | HL | CM) CM* (PR | PO); 192 LB25: ((PR | PO)CM*)? ((OP | HY)CM*)? NU (CM*(NU | SY | IS))* (CM*(CL | CP))? (CM*(PR | PO))?; 200 LB27.3: PR CM* (JL | JV | JT | H2 | H3);
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/external/llvm/lib/Target/X86/ |
H A D | X86TargetMachine.cpp | 41 PassRegistry &PR = *PassRegistry::getPassRegistry(); local 42 initializeWinEHStatePassPass(PR); 43 initializeFixupBWInstPassPass(PR);
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | RegisterScavenging.cpp | 74 BitVector PR = MBB->getParent()->getFrameInfo()->getPristineRegs(MBB); local 75 for (int I = PR.find_first(); I>0; I = PR.find_next(I))
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/external/llvm/tools/llc/ |
H A D | llc.cpp | 403 const PassRegistry *PR = PassRegistry::getPassRegistry(); local 422 const PassInfo *PI = PR->getPassInfo(RunPassName); 446 const PassInfo *PI = PR->getPassInfo(StartAfter); 454 const PassInfo *PI = PR->getPassInfo(StopAfter);
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/external/Microsoft-GSL/ |
H A D | CONTRIBUTING.md | 8 a PR, please post a comment in the associated issue to avoid duplication of effort. 21 * Requests need not be a single commit, but should be a linear sequence of commits (i.e. no merge commits in your PR)
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/external/llvm/lib/CodeGen/ |
H A D | RegisterScavenging.cpp | 58 BitVector PR = MF.getFrameInfo()->getPristineRegs(MF); local 59 for (int I = PR.find_first(); I>0; I = PR.find_next(I))
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/external/llvm/lib/Target/AArch64/ |
H A D | AArch64TargetMachine.cpp | 116 auto PR = PassRegistry::getPassRegistry(); local 117 initializeGlobalISel(*PR); 118 initializeAArch64ExpandPseudoPass(*PR);
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/external/opencv/cv/src/ |
H A D | cvfloodfill.cpp | 144 int k, YC, PL, PR, dir; local 145 ICV_POP( YC, L, R, PL, PR, dir ); 151 {dir, PR + 1, R + _8_connectivity} 276 int k, YC, PL, PR, dir; local 277 ICV_POP( YC, L, R, PL, PR, dir ); 283 {dir, PR + 1, R + _8_connectivity} 453 int k, YC, PL, PR, dir, curstep; local 454 ICV_POP( YC, L, R, PL, PR, dir ); 460 {dir, PR + 1, R + _8_connectivity} 759 int k, YC, PL, PR, di local [all...] |