| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| H A D | RegisterClassInfo.cpp | 71 RCInfo &RCI = RegClass[RC->getID()]; local
76 if (!RCI.Order)
77 RCI.Order.reset(new unsigned[NumRegs]);
94 RCI.Order[N++] = PhysReg;
96 RCI.NumRegs = N + CSRAlias.size();
97 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
100 std::copy(CSRAlias.begin(), CSRAlias.end(), &RCI.Order[N]);
104 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
105 RCI.ProperSubClass = true;
109 for (unsigned I = 0; I != RCI
[all...] |
| H A D | AllocationOrder.cpp | 28 : Begin(0), End(0), Pos(0), RCI(RegClassInfo), OwnedBegin(false) {
55 if (!RCI.isReserved(Order[i]))
65 ArrayRef<unsigned> O = RCI.getOrder(RC);
72 !RC->contains(Hint) || RCI.isReserved(Hint)))
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| H A D | RegisterClassInfo.h | 65 const RCInfo &RCI = RegClass[RC->getID()]; local
66 if (Tag != RCI.Tag)
68 return RCI;
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| H A D | AllocationOrder.h | 29 const RegisterClassInfo &RCI; member in class:llvm::AllocationOrder
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| H A D | AggressiveAntiDepBreaker.h | 134 const RegisterClassInfo &RCI,
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| H A D | PostRASchedulerList.cpp | 185 AliasAnalysis *AA, const RegisterClassInfo &RCI,
197 (AntiDepBreaker *)new AggressiveAntiDepBreaker(MF, RCI, CriticalPathRCs) :
199 (AntiDepBreaker *)new CriticalAntiDepBreaker(MF, RCI) : NULL));
183 SchedulePostRATDList( MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT, AliasAnalysis *AA, const RegisterClassInfo &RCI, TargetSubtargetInfo::AntiDepBreakMode AntiDepMode, SmallVectorImpl<TargetRegisterClass*> &CriticalPathRCs) argument
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| H A D | RegAllocLinearScan.cpp | 407 for (TargetRegisterInfo::regclass_iterator RCI = tri_->regclass_begin(),
408 E = tri_->regclass_end(); RCI != E; ++RCI) {
409 RelatedRegClasses.insert(*RCI);
410 for (TargetRegisterClass::iterator I = (*RCI)->begin(), E = (*RCI)->end();
418 RelatedRegClasses.unionSets(PRC, *RCI);
420 PRC = *RCI;
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| H A D | CriticalAntiDepBreaker.cpp | 30 CriticalAntiDepBreaker(MachineFunction& MFi, const RegisterClassInfo &RCI) : argument
35 RegClassInfo(RCI),
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| H A D | AggressiveAntiDepBreaker.cpp | 118 const RegisterClassInfo &RCI,
124 RegClassInfo(RCI),
117 AggressiveAntiDepBreaker(MachineFunction& MFi, const RegisterClassInfo &RCI, TargetSubtargetInfo::RegClassVector& CriticalPathRCs) argument
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| /external/llvm/lib/CodeGen/ |
| H A D | RegisterClassInfo.cpp | 81 RCInfo &RCI = RegClass[RC->getID()]; local
86 if (!RCI.Order)
87 RCI.Order.reset(new MCPhysReg[NumRegs]);
112 RCI.Order[N++] = PhysReg;
116 RCI.NumRegs = N + CSRAlias.size();
117 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
125 RCI.Order[N++] = PhysReg;
130 if (StressRA && RCI.NumRegs > StressRA)
131 RCI.NumRegs = StressRA;
136 if (Super != RC && getNumAllocatableRegs(Super) > RCI
[all...] |
| H A D | TargetRegisterInfo.cpp | 217 for (SuperRegClassIterator RCI(B, this); RCI.isValid(); ++RCI)
218 if (RCI.getSubReg() == Idx)
221 return firstCommonClass(RCI.getMask(), A->getSubClassMask(), this);
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| H A D | ShrinkWrap.cpp | 101 RegisterClassInfo RCI; member in class:__anon12645::ShrinkWrap
161 RCI.runOnMachineFunction(MF);
238 UseOrDefCSR = RCI.getLastCalleeSavedAlias(PhysReg);
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| H A D | AggressiveAntiDepBreaker.h | 128 const RegisterClassInfo &RCI,
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| H A D | PostRASchedulerList.cpp | 208 const RegisterClassInfo &RCI,
225 (AntiDepBreaker *)new AggressiveAntiDepBreaker(MF, RCI, CriticalPathRCs) :
227 (AntiDepBreaker *)new CriticalAntiDepBreaker(MF, RCI) : nullptr));
206 SchedulePostRATDList( MachineFunction &MF, MachineLoopInfo &MLI, AliasAnalysis *AA, const RegisterClassInfo &RCI, TargetSubtargetInfo::AntiDepBreakMode AntiDepMode, SmallVectorImpl<const TargetRegisterClass *> &CriticalPathRCs) argument
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| H A D | RegisterPressure.cpp | 230 RCI = rci;
920 const RegisterClassInfo *RCI,
930 unsigned Limit = RCI->getRegPressureSetLimit(i);
1064 computeExcessPressureDelta(SavedPressure, CurrSetPressure, Delta, RCI,
1130 unsigned Limit = RCI->getRegPressureSetLimit(PSetID);
1308 computeExcessPressureDelta(SavedPressure, CurrSetPressure, Delta, RCI,
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| H A D | CriticalAntiDepBreaker.cpp | 31 const RegisterClassInfo &RCI)
34 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI),
30 CriticalAntiDepBreaker(MachineFunction &MFi, const RegisterClassInfo &RCI) argument
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| H A D | RegAllocGreedy.cpp | 122 RegisterClassInfo RCI; member in class:__anon12608::RAGreedy
1562 const RegisterClassInfo &RCI) {
1570 return RCI.getNumAllocatableRegs(ConstrainedRC);
1601 unsigned SuperRCNumAllocatableRegs = RCI.getNumAllocatableRegs(SuperRC);
1611 TRI, RCI)) {
2576 RCI.runOnMachineFunction(mf);
1559 getNumAllocatableRegsForConstraints( const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, const RegisterClassInfo &RCI) argument
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| H A D | AggressiveAntiDepBreaker.cpp | 114 MachineFunction &MFi, const RegisterClassInfo &RCI,
118 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI),
113 AggressiveAntiDepBreaker( MachineFunction &MFi, const RegisterClassInfo &RCI, TargetSubtargetInfo::RegClassVector &CriticalPathRCs) argument
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| H A D | TargetLoweringBase.cpp | 1271 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1272 SuperRegRC.setBitsInMask(RCI.getMask());
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 71 const RCInfo &RCI = RegClass[RC->getID()]; local
72 if (Tag != RCI.Tag)
74 return RCI;
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| H A D | RegisterPressure.h | 343 const RegisterClassInfo *RCI;
381 MF(nullptr), TRI(nullptr), RCI(nullptr), LIS(nullptr), MBB(nullptr), P(rp),
385 MF(nullptr), TRI(nullptr), RCI(nullptr), LIS(nullptr), MBB(nullptr), P(rp),
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| /external/llvm/lib/Transforms/Scalar/ |
| H A D | ConstantHoisting.cpp | 149 for (auto const &RCI : ConstInfo.RebasedConstants)
150 for (auto const &U : RCI.Uses)
561 for (auto const &RCI : ConstInfo.RebasedConstants) {
563 for (auto const &U : RCI.Uses)
564 emitBaseConstants(Base, RCI.Offset, U);
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64A57FPLoadBalancing.cpp | 117 RegisterClassInfo RCI; member in class:__anon12798::AArch64A57FPLoadBalancing
326 RCI.runOnMachineFunction(F);
534 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID));
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 2757 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2758 E = RI->regclass_end(); RCI != E; ++RCI) {
2759 const TargetRegisterClass *RC = *RCI;
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | TargetLowering.cpp | 2357 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(),
2358 E = RI->regclass_end(); RCI != E; ++RCI) {
2359 const TargetRegisterClass *RC = *RCI;
|